8955b727af
The HDMI core IP on OMAP5 has a wider address range for registers. The offsets for the later registers can't fit into the u16 type currently used for hdmi register read and write functions. Use u32 for offsets instead. Signed-off-by: Archit Taneja <archit@ti.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
447 lines
12 KiB
C
447 lines
12 KiB
C
/*
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* HDMI driver definition for TI OMAP4 Processor.
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*
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* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _HDMI_H
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#define _HDMI_H
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <video/omapdss.h>
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#include "dss.h"
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/* HDMI Wrapper */
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#define HDMI_WP_REVISION 0x0
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#define HDMI_WP_SYSCONFIG 0x10
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#define HDMI_WP_IRQSTATUS_RAW 0x24
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#define HDMI_WP_IRQSTATUS 0x28
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#define HDMI_WP_IRQENABLE_SET 0x2C
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#define HDMI_WP_IRQENABLE_CLR 0x30
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#define HDMI_WP_IRQWAKEEN 0x34
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#define HDMI_WP_PWR_CTRL 0x40
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#define HDMI_WP_DEBOUNCE 0x44
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#define HDMI_WP_VIDEO_CFG 0x50
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#define HDMI_WP_VIDEO_SIZE 0x60
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#define HDMI_WP_VIDEO_TIMING_H 0x68
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#define HDMI_WP_VIDEO_TIMING_V 0x6C
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#define HDMI_WP_CLK 0x70
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#define HDMI_WP_AUDIO_CFG 0x80
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#define HDMI_WP_AUDIO_CFG2 0x84
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#define HDMI_WP_AUDIO_CTRL 0x88
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#define HDMI_WP_AUDIO_DATA 0x8C
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/* HDMI WP IRQ flags */
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#define HDMI_IRQ_CORE (1 << 0)
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#define HDMI_IRQ_OCP_TIMEOUT (1 << 4)
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#define HDMI_IRQ_AUDIO_FIFO_UNDERFLOW (1 << 8)
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#define HDMI_IRQ_AUDIO_FIFO_OVERFLOW (1 << 9)
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#define HDMI_IRQ_AUDIO_FIFO_SAMPLE_REQ (1 << 10)
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#define HDMI_IRQ_VIDEO_VSYNC (1 << 16)
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#define HDMI_IRQ_VIDEO_FRAME_DONE (1 << 17)
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#define HDMI_IRQ_PHY_LINE5V_ASSERT (1 << 24)
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#define HDMI_IRQ_LINK_CONNECT (1 << 25)
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#define HDMI_IRQ_LINK_DISCONNECT (1 << 26)
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#define HDMI_IRQ_PLL_LOCK (1 << 29)
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#define HDMI_IRQ_PLL_UNLOCK (1 << 30)
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#define HDMI_IRQ_PLL_RECAL (1 << 31)
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/* HDMI PLL */
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#define PLLCTRL_PLL_CONTROL 0x0
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#define PLLCTRL_PLL_STATUS 0x4
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#define PLLCTRL_PLL_GO 0x8
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#define PLLCTRL_CFG1 0xC
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#define PLLCTRL_CFG2 0x10
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#define PLLCTRL_CFG3 0x14
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#define PLLCTRL_SSC_CFG1 0x18
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#define PLLCTRL_SSC_CFG2 0x1C
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#define PLLCTRL_CFG4 0x20
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/* HDMI PHY */
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#define HDMI_TXPHY_TX_CTRL 0x0
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#define HDMI_TXPHY_DIGITAL_CTRL 0x4
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#define HDMI_TXPHY_POWER_CTRL 0x8
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#define HDMI_TXPHY_PAD_CFG_CTRL 0xC
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enum hdmi_pll_pwr {
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HDMI_PLLPWRCMD_ALLOFF = 0,
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HDMI_PLLPWRCMD_PLLONLY = 1,
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HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2,
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HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3
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};
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enum hdmi_phy_pwr {
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HDMI_PHYPWRCMD_OFF = 0,
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HDMI_PHYPWRCMD_LDOON = 1,
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HDMI_PHYPWRCMD_TXON = 2
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};
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enum hdmi_core_hdmi_dvi {
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HDMI_DVI = 0,
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HDMI_HDMI = 1
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};
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enum hdmi_clk_refsel {
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HDMI_REFSEL_PCLK = 0,
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HDMI_REFSEL_REF1 = 1,
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HDMI_REFSEL_REF2 = 2,
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HDMI_REFSEL_SYSCLK = 3
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};
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enum hdmi_packing_mode {
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HDMI_PACK_10b_RGB_YUV444 = 0,
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HDMI_PACK_24b_RGB_YUV444_YUV422 = 1,
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HDMI_PACK_20b_YUV422 = 2,
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HDMI_PACK_ALREADYPACKED = 7
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};
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enum hdmi_stereo_channels {
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HDMI_AUDIO_STEREO_NOCHANNELS = 0,
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HDMI_AUDIO_STEREO_ONECHANNEL = 1,
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HDMI_AUDIO_STEREO_TWOCHANNELS = 2,
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HDMI_AUDIO_STEREO_THREECHANNELS = 3,
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HDMI_AUDIO_STEREO_FOURCHANNELS = 4
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};
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enum hdmi_audio_type {
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HDMI_AUDIO_TYPE_LPCM = 0,
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HDMI_AUDIO_TYPE_IEC = 1
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};
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enum hdmi_audio_justify {
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HDMI_AUDIO_JUSTIFY_LEFT = 0,
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HDMI_AUDIO_JUSTIFY_RIGHT = 1
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};
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enum hdmi_audio_sample_order {
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HDMI_AUDIO_SAMPLE_RIGHT_FIRST = 0,
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HDMI_AUDIO_SAMPLE_LEFT_FIRST = 1
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};
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enum hdmi_audio_samples_perword {
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HDMI_AUDIO_ONEWORD_ONESAMPLE = 0,
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HDMI_AUDIO_ONEWORD_TWOSAMPLES = 1
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};
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enum hdmi_audio_sample_size {
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HDMI_AUDIO_SAMPLE_16BITS = 0,
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HDMI_AUDIO_SAMPLE_24BITS = 1
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};
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enum hdmi_audio_transf_mode {
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HDMI_AUDIO_TRANSF_DMA = 0,
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HDMI_AUDIO_TRANSF_IRQ = 1
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};
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enum hdmi_audio_blk_strt_end_sig {
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HDMI_AUDIO_BLOCK_SIG_STARTEND_ON = 0,
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HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF = 1
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};
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enum hdmi_core_audio_layout {
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HDMI_AUDIO_LAYOUT_2CH = 0,
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HDMI_AUDIO_LAYOUT_8CH = 1
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};
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enum hdmi_core_cts_mode {
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HDMI_AUDIO_CTS_MODE_HW = 0,
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HDMI_AUDIO_CTS_MODE_SW = 1
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};
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enum hdmi_audio_mclk_mode {
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HDMI_AUDIO_MCLK_128FS = 0,
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HDMI_AUDIO_MCLK_256FS = 1,
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HDMI_AUDIO_MCLK_384FS = 2,
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HDMI_AUDIO_MCLK_512FS = 3,
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HDMI_AUDIO_MCLK_768FS = 4,
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HDMI_AUDIO_MCLK_1024FS = 5,
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HDMI_AUDIO_MCLK_1152FS = 6,
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HDMI_AUDIO_MCLK_192FS = 7
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};
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/* INFOFRAME_AVI_ and INFOFRAME_AUDIO_ definitions */
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enum hdmi_core_infoframe {
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HDMI_INFOFRAME_AVI_DB1Y_RGB = 0,
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HDMI_INFOFRAME_AVI_DB1Y_YUV422 = 1,
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HDMI_INFOFRAME_AVI_DB1Y_YUV444 = 2,
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HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF = 0,
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HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_ON = 1,
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HDMI_INFOFRAME_AVI_DB1B_NO = 0,
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HDMI_INFOFRAME_AVI_DB1B_VERT = 1,
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HDMI_INFOFRAME_AVI_DB1B_HORI = 2,
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HDMI_INFOFRAME_AVI_DB1B_VERTHORI = 3,
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HDMI_INFOFRAME_AVI_DB1S_0 = 0,
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HDMI_INFOFRAME_AVI_DB1S_1 = 1,
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HDMI_INFOFRAME_AVI_DB1S_2 = 2,
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HDMI_INFOFRAME_AVI_DB2C_NO = 0,
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HDMI_INFOFRAME_AVI_DB2C_ITU601 = 1,
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HDMI_INFOFRAME_AVI_DB2C_ITU709 = 2,
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HDMI_INFOFRAME_AVI_DB2C_EC_EXTENDED = 3,
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HDMI_INFOFRAME_AVI_DB2M_NO = 0,
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HDMI_INFOFRAME_AVI_DB2M_43 = 1,
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HDMI_INFOFRAME_AVI_DB2M_169 = 2,
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HDMI_INFOFRAME_AVI_DB2R_SAME = 8,
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HDMI_INFOFRAME_AVI_DB2R_43 = 9,
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HDMI_INFOFRAME_AVI_DB2R_169 = 10,
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HDMI_INFOFRAME_AVI_DB2R_149 = 11,
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HDMI_INFOFRAME_AVI_DB3ITC_NO = 0,
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HDMI_INFOFRAME_AVI_DB3ITC_YES = 1,
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HDMI_INFOFRAME_AVI_DB3EC_XVYUV601 = 0,
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HDMI_INFOFRAME_AVI_DB3EC_XVYUV709 = 1,
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HDMI_INFOFRAME_AVI_DB3Q_DEFAULT = 0,
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HDMI_INFOFRAME_AVI_DB3Q_LR = 1,
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HDMI_INFOFRAME_AVI_DB3Q_FR = 2,
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HDMI_INFOFRAME_AVI_DB3SC_NO = 0,
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HDMI_INFOFRAME_AVI_DB3SC_HORI = 1,
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HDMI_INFOFRAME_AVI_DB3SC_VERT = 2,
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HDMI_INFOFRAME_AVI_DB3SC_HORIVERT = 3,
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HDMI_INFOFRAME_AVI_DB5PR_NO = 0,
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HDMI_INFOFRAME_AVI_DB5PR_2 = 1,
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HDMI_INFOFRAME_AVI_DB5PR_3 = 2,
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HDMI_INFOFRAME_AVI_DB5PR_4 = 3,
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HDMI_INFOFRAME_AVI_DB5PR_5 = 4,
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HDMI_INFOFRAME_AVI_DB5PR_6 = 5,
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HDMI_INFOFRAME_AVI_DB5PR_7 = 6,
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HDMI_INFOFRAME_AVI_DB5PR_8 = 7,
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HDMI_INFOFRAME_AVI_DB5PR_9 = 8,
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HDMI_INFOFRAME_AVI_DB5PR_10 = 9,
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};
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struct hdmi_cm {
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int code;
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int mode;
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};
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struct hdmi_video_format {
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enum hdmi_packing_mode packing_mode;
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u32 y_res; /* Line per panel */
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u32 x_res; /* pixel per line */
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};
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struct hdmi_config {
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struct omap_video_timings timings;
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struct hdmi_cm cm;
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};
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/* HDMI PLL structure */
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struct hdmi_pll_info {
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u16 regn;
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u16 regm;
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u32 regmf;
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u16 regm2;
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u16 regsd;
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u16 dcofreq;
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enum hdmi_clk_refsel refsel;
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};
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struct hdmi_audio_format {
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enum hdmi_stereo_channels stereo_channels;
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u8 active_chnnls_msk;
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enum hdmi_audio_type type;
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enum hdmi_audio_justify justification;
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enum hdmi_audio_sample_order sample_order;
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enum hdmi_audio_samples_perword samples_per_word;
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enum hdmi_audio_sample_size sample_size;
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enum hdmi_audio_blk_strt_end_sig en_sig_blk_strt_end;
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};
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struct hdmi_audio_dma {
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u8 transfer_size;
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u8 block_size;
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enum hdmi_audio_transf_mode mode;
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u16 fifo_threshold;
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};
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struct hdmi_core_audio_i2s_config {
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u8 in_length_bits;
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u8 justification;
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u8 sck_edge_mode;
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u8 vbit;
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u8 direction;
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u8 shift;
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u8 active_sds;
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};
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struct hdmi_core_audio_config {
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struct hdmi_core_audio_i2s_config i2s_cfg;
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struct snd_aes_iec958 *iec60958_cfg;
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bool fs_override;
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u32 n;
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u32 cts;
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u32 aud_par_busclk;
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enum hdmi_core_audio_layout layout;
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enum hdmi_core_cts_mode cts_mode;
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bool use_mclk;
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enum hdmi_audio_mclk_mode mclk_mode;
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bool en_acr_pkt;
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bool en_dsd_audio;
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bool en_parallel_aud_input;
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bool en_spdif;
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};
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/*
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* Refer to section 8.2 in HDMI 1.3 specification for
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* details about infoframe databytes
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*/
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struct hdmi_core_infoframe_avi {
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/* Y0, Y1 rgb,yCbCr */
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u8 db1_format;
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/* A0 Active information Present */
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u8 db1_active_info;
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/* B0, B1 Bar info data valid */
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u8 db1_bar_info_dv;
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/* S0, S1 scan information */
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u8 db1_scan_info;
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/* C0, C1 colorimetry */
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u8 db2_colorimetry;
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/* M0, M1 Aspect ratio (4:3, 16:9) */
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u8 db2_aspect_ratio;
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/* R0...R3 Active format aspect ratio */
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u8 db2_active_fmt_ar;
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/* ITC IT content. */
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u8 db3_itc;
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/* EC0, EC1, EC2 Extended colorimetry */
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u8 db3_ec;
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/* Q1, Q0 Quantization range */
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u8 db3_q_range;
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/* SC1, SC0 Non-uniform picture scaling */
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u8 db3_nup_scaling;
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/* VIC0..6 Video format identification */
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u8 db4_videocode;
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/* PR0..PR3 Pixel repetition factor */
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u8 db5_pixel_repeat;
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/* Line number end of top bar */
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u16 db6_7_line_eoftop;
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/* Line number start of bottom bar */
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u16 db8_9_line_sofbottom;
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/* Pixel number end of left bar */
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u16 db10_11_pixel_eofleft;
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/* Pixel number start of right bar */
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u16 db12_13_pixel_sofright;
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};
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struct hdmi_wp_data {
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void __iomem *base;
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};
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struct hdmi_pll_data {
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void __iomem *base;
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struct hdmi_pll_info info;
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};
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struct hdmi_phy_data {
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void __iomem *base;
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u8 lane_function[4];
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u8 lane_polarity[4];
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};
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struct hdmi_core_data {
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void __iomem *base;
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struct hdmi_core_infoframe_avi avi_cfg;
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};
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static inline void hdmi_write_reg(void __iomem *base_addr, const u32 idx,
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u32 val)
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{
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__raw_writel(val, base_addr + idx);
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}
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static inline u32 hdmi_read_reg(void __iomem *base_addr, const u32 idx)
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{
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return __raw_readl(base_addr + idx);
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}
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#define REG_FLD_MOD(base, idx, val, start, end) \
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hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\
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val, start, end))
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#define REG_GET(base, idx, start, end) \
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FLD_GET(hdmi_read_reg(base, idx), start, end)
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static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,
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const u32 idx, int b2, int b1, u32 val)
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{
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u32 t = 0, v;
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while (val != (v = REG_GET(base_addr, idx, b2, b1))) {
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if (t++ > 10000)
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return v;
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udelay(1);
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}
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return v;
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}
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/* HDMI wrapper funcs */
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int hdmi_wp_video_start(struct hdmi_wp_data *wp);
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void hdmi_wp_video_stop(struct hdmi_wp_data *wp);
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void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s);
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u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp);
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void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus);
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void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask);
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void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask);
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int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val);
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int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val);
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void hdmi_wp_video_config_format(struct hdmi_wp_data *wp,
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struct hdmi_video_format *video_fmt);
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void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,
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struct omap_video_timings *timings);
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void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,
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struct omap_video_timings *timings);
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void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt,
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struct omap_video_timings *timings, struct hdmi_config *param);
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int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp);
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/* HDMI PLL funcs */
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int hdmi_pll_enable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp);
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void hdmi_pll_disable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp);
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void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s);
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void hdmi_pll_compute(struct hdmi_pll_data *pll, unsigned long clkin, int phy);
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int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll);
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/* HDMI PHY funcs */
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int hdmi_phy_configure(struct hdmi_phy_data *phy, struct hdmi_config *cfg);
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void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s);
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int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy);
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int hdmi_phy_parse_lanes(struct hdmi_phy_data *phy, const u32 *lanes);
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/* HDMI common funcs */
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const struct hdmi_config *hdmi_default_timing(void);
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const struct hdmi_config *hdmi_get_timings(int mode, int code);
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struct hdmi_cm hdmi_get_code(struct omap_video_timings *timing);
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int hdmi_parse_lanes_of(struct platform_device *pdev, struct device_node *ep,
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struct hdmi_phy_data *phy);
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#if defined(CONFIG_OMAP4_DSS_HDMI_AUDIO)
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int hdmi_compute_acr(u32 pclk, u32 sample_freq, u32 *n, u32 *cts);
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int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable);
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int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable);
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void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp,
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struct hdmi_audio_format *aud_fmt);
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void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp,
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struct hdmi_audio_dma *aud_dma);
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static inline bool hdmi_mode_has_audio(int mode)
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{
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return mode == HDMI_HDMI ? true : false;
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}
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#endif
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#endif
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