3af36706ff
The SKL driver does not code DSP topology in driver. It uses the newly added ASoC topology core to parse the topology information (controls, widgets and map) from topology binary. Each topology element passed private data which contains information that driver used to identify the module instance within firmware and send IPCs for that module to DSP firmware along with parameters. This patch adds init routine to invoke topology load and callback for topology creation. Signed-off-by: Jeeja KP <jeeja.kp@intel.com> Signed-off-by: Subhransu S. Prusty <subhransu.s.prusty@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
169 lines
3.8 KiB
C
169 lines
3.8 KiB
C
/*
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* skl-tplg-interface.h - Intel DSP FW private data interface
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*
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* Copyright (C) 2015 Intel Corp
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* Author: Jeeja KP <jeeja.kp@intel.com>
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* Nilofer, Samreen <samreen.nilofer@intel.com>
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*/
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#ifndef __HDA_TPLG_INTERFACE_H__
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#define __HDA_TPLG_INTERFACE_H__
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/*
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* Default types range from 0~12. type can range from 0 to 0xff
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* SST types start at higher to avoid any overlapping in future
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*/
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#define SOC_CONTROL_TYPE_HDA_SST_ALGO_PARAMS 0x100
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#define SOC_CONTROL_TYPE_HDA_SST_MUX 0x101
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#define SOC_CONTROL_TYPE_HDA_SST_MIX 0x101
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#define SOC_CONTROL_TYPE_HDA_SST_BYTE 0x103
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#define HDA_SST_CFG_MAX 900 /* size of copier cfg*/
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#define MAX_IN_QUEUE 8
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#define MAX_OUT_QUEUE 8
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/* Event types goes here */
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/* Reserve event type 0 for no event handlers */
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enum skl_event_types {
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SKL_EVENT_NONE = 0,
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SKL_MIXER_EVENT,
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SKL_MUX_EVENT,
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SKL_VMIXER_EVENT,
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SKL_PGA_EVENT
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};
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/**
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* enum skl_ch_cfg - channel configuration
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*
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* @SKL_CH_CFG_MONO: One channel only
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* @SKL_CH_CFG_STEREO: L & R
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* @SKL_CH_CFG_2_1: L, R & LFE
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* @SKL_CH_CFG_3_0: L, C & R
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* @SKL_CH_CFG_3_1: L, C, R & LFE
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* @SKL_CH_CFG_QUATRO: L, R, Ls & Rs
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* @SKL_CH_CFG_4_0: L, C, R & Cs
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* @SKL_CH_CFG_5_0: L, C, R, Ls & Rs
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* @SKL_CH_CFG_5_1: L, C, R, Ls, Rs & LFE
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* @SKL_CH_CFG_DUAL_MONO: One channel replicated in two
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* @SKL_CH_CFG_I2S_DUAL_STEREO_0: Stereo(L,R) in 4 slots, 1st stream:[ L, R, -, - ]
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* @SKL_CH_CFG_I2S_DUAL_STEREO_1: Stereo(L,R) in 4 slots, 2nd stream:[ -, -, L, R ]
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* @SKL_CH_CFG_INVALID: Invalid
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*/
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enum skl_ch_cfg {
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SKL_CH_CFG_MONO = 0,
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SKL_CH_CFG_STEREO = 1,
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SKL_CH_CFG_2_1 = 2,
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SKL_CH_CFG_3_0 = 3,
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SKL_CH_CFG_3_1 = 4,
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SKL_CH_CFG_QUATRO = 5,
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SKL_CH_CFG_4_0 = 6,
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SKL_CH_CFG_5_0 = 7,
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SKL_CH_CFG_5_1 = 8,
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SKL_CH_CFG_DUAL_MONO = 9,
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SKL_CH_CFG_I2S_DUAL_STEREO_0 = 10,
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SKL_CH_CFG_I2S_DUAL_STEREO_1 = 11,
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SKL_CH_CFG_INVALID
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};
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enum skl_module_type {
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SKL_MODULE_TYPE_MIXER = 0,
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SKL_MODULE_TYPE_COPIER,
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SKL_MODULE_TYPE_UPDWMIX,
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SKL_MODULE_TYPE_SRCINT
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};
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enum skl_core_affinity {
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SKL_AFFINITY_CORE_0 = 0,
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SKL_AFFINITY_CORE_1,
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SKL_AFFINITY_CORE_MAX
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};
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enum skl_pipe_conn_type {
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SKL_PIPE_CONN_TYPE_NONE = 0,
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SKL_PIPE_CONN_TYPE_FE,
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SKL_PIPE_CONN_TYPE_BE
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};
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enum skl_hw_conn_type {
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SKL_CONN_NONE = 0,
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SKL_CONN_SOURCE = 1,
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SKL_CONN_SINK = 2
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};
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enum skl_dev_type {
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SKL_DEVICE_BT = 0x0,
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SKL_DEVICE_DMIC = 0x1,
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SKL_DEVICE_I2S = 0x2,
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SKL_DEVICE_SLIMBUS = 0x3,
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SKL_DEVICE_HDALINK = 0x4,
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SKL_DEVICE_NONE
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};
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struct skl_dfw_module_pin {
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u16 module_id;
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u16 instance_id;
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u8 pin_id;
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bool is_dynamic;
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} __packed;
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struct skl_dfw_module_fmt {
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u32 channels;
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u32 freq;
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u32 bit_depth;
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u32 valid_bit_depth;
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u32 ch_cfg;
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} __packed;
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struct skl_dfw_module_caps {
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u32 caps_size;
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u32 caps[HDA_SST_CFG_MAX];
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};
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struct skl_dfw_pipe {
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u8 pipe_id;
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u8 pipe_priority;
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u16 conn_type;
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u32 memory_pages;
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} __packed;
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struct skl_dfw_module {
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u16 module_id;
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u16 instance_id;
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u32 max_mcps;
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u8 core_id;
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u8 max_in_queue;
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u8 max_out_queue;
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u8 is_loadable;
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u8 conn_type;
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u8 dev_type;
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u8 hw_conn_type;
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u8 time_slot;
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u32 obs;
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u32 ibs;
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u32 params_fixup;
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u32 converter;
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u32 module_type;
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u32 vbus_id;
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struct skl_dfw_pipe pipe;
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struct skl_dfw_module_fmt in_fmt;
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struct skl_dfw_module_fmt out_fmt;
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struct skl_dfw_module_caps caps;
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} __packed;
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struct skl_dfw_algo_data {
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u32 max;
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char *params;
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} __packed;
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#endif
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