846fdf2a3d
The legacy support is wrong and dangerous, as it doesn't take any OPPs into account and does not scale voltages. Switching mpurate should be handled through cpufreq. Signed-off-by: Tero Kristo <t-kristo@ti.com>
111 lines
3.3 KiB
C
111 lines
3.3 KiB
C
/*
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* OMAP3-specific clock framework functions
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*
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* Copyright (C) 2007-2008 Texas Instruments, Inc.
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* Copyright (C) 2007-2010 Nokia Corporation
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*
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* Paul Walmsley
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* Jouni Högander
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*
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* Parts of this code are based on code written by
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* Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#undef DEBUG
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include "soc.h"
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#include "clock.h"
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#include "clock3xxx.h"
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#include "prm2xxx_3xxx.h"
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#include "prm-regbits-34xx.h"
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#include "cm2xxx_3xxx.h"
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#include "cm-regbits-34xx.h"
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/*
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* DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
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* that are sourced by DPLL5, and both of these require this clock
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* to be at 120 MHz for proper operation.
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*/
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#define DPLL5_FREQ_FOR_USBHOST 120000000
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/* needed by omap3_core_dpll_m2_set_rate() */
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struct clk *sdrc_ick_p, *arm_fck_p;
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/**
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* omap3_dpll4_set_rate - set rate for omap3 per-dpll
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* @hw: clock to change
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* @rate: target rate for clock
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* @parent_rate: rate of the parent clock
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*
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* Check if the current SoC supports the per-dpll reprogram operation
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* or not, and then do the rate change if supported. Returns -EINVAL
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* if not supported, 0 for success, and potential error codes from the
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* clock rate change.
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*/
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int omap3_dpll4_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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/*
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* According to the 12-5 CDP code from TI, "Limitation 2.5"
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* on 3430ES1 prevents us from changing DPLL multipliers or dividers
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* on DPLL4.
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*/
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if (ti_clk_get_features()->flags & TI_CLK_DPLL4_DENY_REPROGRAM) {
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pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n");
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return -EINVAL;
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}
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return omap3_noncore_dpll_set_rate(hw, rate, parent_rate);
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}
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/**
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* omap3_dpll4_set_rate_and_parent - set rate and parent for omap3 per-dpll
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* @hw: clock to change
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* @rate: target rate for clock
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* @parent_rate: rate of the parent clock
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* @index: parent index, 0 - reference clock, 1 - bypass clock
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*
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* Check if the current SoC support the per-dpll reprogram operation
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* or not, and then do the rate + parent change if supported. Returns
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* -EINVAL if not supported, 0 for success, and potential error codes
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* from the clock rate change.
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*/
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int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate, u8 index)
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{
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if (ti_clk_get_features()->flags & TI_CLK_DPLL4_DENY_REPROGRAM) {
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pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n");
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return -EINVAL;
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}
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return omap3_noncore_dpll_set_rate_and_parent(hw, rate, parent_rate,
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index);
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}
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void __init omap3_clk_lock_dpll5(void)
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{
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struct clk *dpll5_clk;
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struct clk *dpll5_m2_clk;
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dpll5_clk = clk_get(NULL, "dpll5_ck");
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clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
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clk_prepare_enable(dpll5_clk);
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/* Program dpll5_m2_clk divider for no division */
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dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
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clk_prepare_enable(dpll5_m2_clk);
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clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);
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clk_disable_unprepare(dpll5_m2_clk);
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clk_disable_unprepare(dpll5_clk);
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return;
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}
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