4cf781c24c
Updated UMC 6.1 function set to support UMC 6.1.1 and 6.1.2 devices Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
53 lines
2.2 KiB
C
53 lines
2.2 KiB
C
/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __UMC_V6_1_H__
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#define __UMC_V6_1_H__
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#include "soc15_common.h"
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#include "amdgpu.h"
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/* HBM Memory Channel Width */
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#define UMC_V6_1_HBM_MEMORY_CHANNEL_WIDTH 128
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/* number of umc channel instance with memory map register access */
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#define UMC_V6_1_CHANNEL_INSTANCE_NUM 4
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/* number of umc instance with memory map register access */
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#define UMC_V6_1_UMC_INSTANCE_NUM 8
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/* total channel instances in one umc block */
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#define UMC_V6_1_TOTAL_CHANNEL_NUM (UMC_V6_1_CHANNEL_INSTANCE_NUM * UMC_V6_1_UMC_INSTANCE_NUM)
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/* UMC regiser per channel offset */
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#define UMC_V6_1_PER_CHANNEL_OFFSET_VG20 0x800
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#define UMC_V6_1_PER_CHANNEL_OFFSET_ARCT 0x400
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/* EccErrCnt max value */
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#define UMC_V6_1_CE_CNT_MAX 0xffff
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/* umc ce interrupt threshold */
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#define UMC_V6_1_CE_INT_THRESHOLD 0xffff
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/* umc ce count initial value */
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#define UMC_V6_1_CE_CNT_INIT (UMC_V6_1_CE_CNT_MAX - UMC_V6_1_CE_INT_THRESHOLD)
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extern const struct amdgpu_umc_funcs umc_v6_1_funcs;
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extern const uint32_t
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umc_v6_1_channel_idx_tbl[UMC_V6_1_UMC_INSTANCE_NUM][UMC_V6_1_CHANNEL_INSTANCE_NUM];
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#endif
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