82b44496ab
This defines __smp_xxx barriers for s390, for use by virtualization. Some smp_xxx barriers are removed as they are defined correctly by asm-generic/barriers.h Note: smp_mb, smp_rmb and smp_wmb are defined as full barriers unconditionally on this architecture. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Martin Schwidefsky <schwidefsky@de.ibm.com> Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
54 lines
1.2 KiB
C
54 lines
1.2 KiB
C
/*
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* Copyright IBM Corp. 1999, 2009
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*
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* Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
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*/
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#ifndef __ASM_BARRIER_H
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#define __ASM_BARRIER_H
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/*
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* Force strict CPU ordering.
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* And yes, this is required on UP too when we're talking
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* to devices.
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*/
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#ifdef CONFIG_HAVE_MARCH_Z196_FEATURES
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/* Fast-BCR without checkpoint synchronization */
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#define __ASM_BARRIER "bcr 14,0\n"
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#else
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#define __ASM_BARRIER "bcr 15,0\n"
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#endif
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#define mb() do { asm volatile(__ASM_BARRIER : : : "memory"); } while (0)
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#define rmb() barrier()
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#define wmb() barrier()
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#define dma_rmb() mb()
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#define dma_wmb() mb()
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#define __smp_mb() mb()
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#define __smp_rmb() rmb()
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#define __smp_wmb() wmb()
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#define smp_mb() __smp_mb()
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#define smp_rmb() __smp_rmb()
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#define smp_wmb() __smp_wmb()
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#define __smp_store_release(p, v) \
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do { \
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compiletime_assert_atomic_type(*p); \
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barrier(); \
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WRITE_ONCE(*p, v); \
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} while (0)
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#define __smp_load_acquire(p) \
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({ \
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typeof(*p) ___p1 = READ_ONCE(*p); \
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compiletime_assert_atomic_type(*p); \
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barrier(); \
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___p1; \
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})
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#include <asm-generic/barrier.h>
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#endif /* __ASM_BARRIER_H */
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