forked from Minki/linux
372 lines
10 KiB
C
372 lines
10 KiB
C
/*
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* sata_sis.c - Silicon Integrated Systems SATA
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*
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* Maintained by: Uwe Koziolek
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* Please ALWAYS copy linux-ide@vger.kernel.org
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* on emails.
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*
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* Copyright 2004 Uwe Koziolek
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*
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* libata documentation is available via 'make {ps|pdf}docs',
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* as Documentation/DocBook/libata.*
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*
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* Hardware documentation available under NDA.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/device.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#include "sis.h"
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#define DRV_NAME "sata_sis"
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#define DRV_VERSION "0.8"
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enum {
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sis_180 = 0,
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SIS_SCR_PCI_BAR = 5,
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/* PCI configuration registers */
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SIS_GENCTL = 0x54, /* IDE General Control register */
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SIS_SCR_BASE = 0xc0, /* sata0 phy SCR registers */
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SIS180_SATA1_OFS = 0x10, /* offset from sata0->sata1 phy regs */
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SIS182_SATA1_OFS = 0x20, /* offset from sata0->sata1 phy regs */
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SIS_PMR = 0x90, /* port mapping register */
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SIS_PMR_COMBINED = 0x30,
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/* random bits */
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SIS_FLAG_CFGSCR = (1 << 30), /* host flag: SCRs via PCI cfg */
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GENCTL_IOMAPPED_SCR = (1 << 26), /* if set, SCRs are in IO space */
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};
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static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
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static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg);
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static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
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static const struct pci_device_id sis_pci_tbl[] = {
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{ PCI_VDEVICE(SI, 0x0180), sis_180 }, /* SiS 964/180 */
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{ PCI_VDEVICE(SI, 0x0181), sis_180 }, /* SiS 964/180 */
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{ PCI_VDEVICE(SI, 0x0182), sis_180 }, /* SiS 965/965L */
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{ PCI_VDEVICE(SI, 0x0183), sis_180 }, /* SiS 965/965L */
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{ PCI_VDEVICE(SI, 0x1182), sis_180 }, /* SiS 966/966L */
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{ PCI_VDEVICE(SI, 0x1183), sis_180 }, /* SiS 966/966L */
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{ } /* terminate list */
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};
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static struct pci_driver sis_pci_driver = {
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.name = DRV_NAME,
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.id_table = sis_pci_tbl,
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.probe = sis_init_one,
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.remove = ata_pci_remove_one,
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};
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static struct scsi_host_template sis_sht = {
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.module = THIS_MODULE,
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.name = DRV_NAME,
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.ioctl = ata_scsi_ioctl,
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.queuecommand = ata_scsi_queuecmd,
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.can_queue = ATA_DEF_QUEUE,
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.this_id = ATA_SHT_THIS_ID,
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.sg_tablesize = ATA_MAX_PRD,
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.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
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.emulated = ATA_SHT_EMULATED,
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.use_clustering = ATA_SHT_USE_CLUSTERING,
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.proc_name = DRV_NAME,
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.dma_boundary = ATA_DMA_BOUNDARY,
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.slave_configure = ata_scsi_slave_config,
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.slave_destroy = ata_scsi_slave_destroy,
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.bios_param = ata_std_bios_param,
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};
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static const struct ata_port_operations sis_ops = {
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.port_disable = ata_port_disable,
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.tf_load = ata_tf_load,
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.tf_read = ata_tf_read,
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.check_status = ata_check_status,
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.exec_command = ata_exec_command,
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.dev_select = ata_std_dev_select,
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.bmdma_setup = ata_bmdma_setup,
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.bmdma_start = ata_bmdma_start,
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.bmdma_stop = ata_bmdma_stop,
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.bmdma_status = ata_bmdma_status,
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.qc_prep = ata_qc_prep,
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.qc_issue = ata_qc_issue_prot,
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.data_xfer = ata_data_xfer,
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.freeze = ata_bmdma_freeze,
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.thaw = ata_bmdma_thaw,
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.error_handler = ata_bmdma_error_handler,
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.post_internal_cmd = ata_bmdma_post_internal_cmd,
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.irq_clear = ata_bmdma_irq_clear,
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.irq_on = ata_irq_on,
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.irq_ack = ata_irq_ack,
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.scr_read = sis_scr_read,
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.scr_write = sis_scr_write,
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.port_start = ata_port_start,
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};
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static const struct ata_port_info sis_port_info = {
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.flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
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.pio_mask = 0x1f,
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.mwdma_mask = 0x7,
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.udma_mask = 0x7f,
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.port_ops = &sis_ops,
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};
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MODULE_AUTHOR("Uwe Koziolek");
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MODULE_DESCRIPTION("low-level driver for Silicon Integratad Systems SATA controller");
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MODULE_LICENSE("GPL");
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MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
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MODULE_VERSION(DRV_VERSION);
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static unsigned int get_scr_cfg_addr(struct ata_port *ap, unsigned int sc_reg)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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unsigned int addr = SIS_SCR_BASE + (4 * sc_reg);
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u8 pmr;
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if (ap->port_no) {
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switch (pdev->device) {
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case 0x0180:
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case 0x0181:
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pci_read_config_byte(pdev, SIS_PMR, &pmr);
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if ((pmr & SIS_PMR_COMBINED) == 0)
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addr += SIS180_SATA1_OFS;
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break;
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case 0x0182:
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case 0x0183:
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case 0x1182:
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case 0x1183:
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addr += SIS182_SATA1_OFS;
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break;
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}
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}
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return addr;
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}
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static u32 sis_scr_cfg_read (struct ata_port *ap, unsigned int sc_reg)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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unsigned int cfg_addr = get_scr_cfg_addr(ap, sc_reg);
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u32 val, val2 = 0;
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u8 pmr;
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if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
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return 0xffffffff;
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pci_read_config_byte(pdev, SIS_PMR, &pmr);
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pci_read_config_dword(pdev, cfg_addr, &val);
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if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) ||
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(pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED))
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pci_read_config_dword(pdev, cfg_addr+0x10, &val2);
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return (val|val2) & 0xfffffffb; /* avoid problems with powerdowned ports */
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}
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static void sis_scr_cfg_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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unsigned int cfg_addr = get_scr_cfg_addr(ap, sc_reg);
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u8 pmr;
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if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
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return;
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pci_read_config_byte(pdev, SIS_PMR, &pmr);
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pci_write_config_dword(pdev, cfg_addr, val);
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if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) ||
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(pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED))
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pci_write_config_dword(pdev, cfg_addr+0x10, val);
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}
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static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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u32 val, val2 = 0;
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u8 pmr;
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if (sc_reg > SCR_CONTROL)
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return 0xffffffffU;
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if (ap->flags & SIS_FLAG_CFGSCR)
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return sis_scr_cfg_read(ap, sc_reg);
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pci_read_config_byte(pdev, SIS_PMR, &pmr);
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val = ioread32(ap->ioaddr.scr_addr + (sc_reg * 4));
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if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) ||
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(pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED))
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val2 = ioread32(ap->ioaddr.scr_addr + (sc_reg * 4) + 0x10);
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return (val | val2) & 0xfffffffb;
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}
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static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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u8 pmr;
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if (sc_reg > SCR_CONTROL)
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return;
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pci_read_config_byte(pdev, SIS_PMR, &pmr);
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if (ap->flags & SIS_FLAG_CFGSCR)
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sis_scr_cfg_write(ap, sc_reg, val);
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else {
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iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4));
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if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) ||
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(pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED))
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iowrite32(val, ap->ioaddr.scr_addr + (sc_reg * 4)+0x10);
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}
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}
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static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
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{
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static int printed_version;
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struct ata_port_info pi = sis_port_info;
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const struct ata_port_info *ppi[] = { &pi, NULL };
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struct ata_host *host;
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u32 genctl, val;
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u8 pmr;
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u8 port2_start = 0x20;
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int rc;
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if (!printed_version++)
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dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
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rc = pcim_enable_device(pdev);
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if (rc)
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return rc;
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/* check and see if the SCRs are in IO space or PCI cfg space */
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pci_read_config_dword(pdev, SIS_GENCTL, &genctl);
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if ((genctl & GENCTL_IOMAPPED_SCR) == 0)
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pi.flags |= SIS_FLAG_CFGSCR;
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/* if hardware thinks SCRs are in IO space, but there are
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* no IO resources assigned, change to PCI cfg space.
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*/
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if ((!(pi.flags & SIS_FLAG_CFGSCR)) &&
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((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) ||
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(pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) {
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genctl &= ~GENCTL_IOMAPPED_SCR;
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pci_write_config_dword(pdev, SIS_GENCTL, genctl);
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pi.flags |= SIS_FLAG_CFGSCR;
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}
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pci_read_config_byte(pdev, SIS_PMR, &pmr);
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switch (ent->device) {
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case 0x0180:
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case 0x0181:
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/* The PATA-handling is provided by pata_sis */
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switch (pmr & 0x30) {
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case 0x10:
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ppi[1] = &sis_info133;
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break;
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case 0x30:
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ppi[0] = &sis_info133;
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break;
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}
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if ((pmr & SIS_PMR_COMBINED) == 0) {
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dev_printk(KERN_INFO, &pdev->dev,
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"Detected SiS 180/181/964 chipset in SATA mode\n");
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port2_start = 64;
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} else {
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dev_printk(KERN_INFO, &pdev->dev,
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"Detected SiS 180/181 chipset in combined mode\n");
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port2_start=0;
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pi.flags |= ATA_FLAG_SLAVE_POSS;
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}
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break;
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case 0x0182:
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case 0x0183:
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pci_read_config_dword ( pdev, 0x6C, &val);
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if (val & (1L << 31)) {
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dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 182/965 chipset\n");
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pi.flags |= ATA_FLAG_SLAVE_POSS;
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} else {
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dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 182/965L chipset\n");
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}
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break;
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case 0x1182:
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case 0x1183:
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pci_read_config_dword(pdev, 0x64, &val);
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if (val & 0x10000000) {
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dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 1182/1183/966L SATA controller\n");
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} else {
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dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 1182/1183/966 SATA controller\n");
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pi.flags |= ATA_FLAG_SLAVE_POSS;
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}
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break;
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}
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rc = ata_pci_prepare_native_host(pdev, ppi, &host);
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if (rc)
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return rc;
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if (!(pi.flags & SIS_FLAG_CFGSCR)) {
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void __iomem *mmio;
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rc = pcim_iomap_regions(pdev, 1 << SIS_SCR_PCI_BAR, DRV_NAME);
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if (rc)
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return rc;
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mmio = host->iomap[SIS_SCR_PCI_BAR];
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host->ports[0]->ioaddr.scr_addr = mmio;
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host->ports[1]->ioaddr.scr_addr = mmio + port2_start;
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}
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pci_set_master(pdev);
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pci_intx(pdev, 1);
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return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED,
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&sis_sht);
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}
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static int __init sis_init(void)
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{
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return pci_register_driver(&sis_pci_driver);
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}
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static void __exit sis_exit(void)
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{
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pci_unregister_driver(&sis_pci_driver);
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}
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module_init(sis_init);
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module_exit(sis_exit);
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