forked from Minki/linux
8041dfbd31
Add interrupt controller driver to the Conexant CX92755 SoC, part of the Digicolor SoCs series. Use the generic irq framework support. Use syscon to access the system global UC_IRQ_CONTROL register. Signed-off-by: Baruch Siach <baruch@tkos.co.il> Cc: linux-arm-kernel@lists.infradead.org Cc: Arnd Bergmann <arnd@arndb.de> Cc: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Jason Cooper <jason@lakedaemon.net> Link: http://lkml.kernel.org/r/5b769e3c23dfa5fde08c4f3bc966c2c2b3921d8a.1421317616.git.baruch@tkos.co.il Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
121 lines
3.2 KiB
C
121 lines
3.2 KiB
C
/*
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* Conexant Digicolor SoCs IRQ chip driver
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*
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* Author: Baruch Siach <baruch@tkos.co.il>
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*
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* Copyright (C) 2014 Paradox Innovation Ltd.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include <asm/exception.h>
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#include "irqchip.h"
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#define UC_IRQ_CONTROL 0x04
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#define IC_FLAG_CLEAR_LO 0x00
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#define IC_FLAG_CLEAR_XLO 0x04
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#define IC_INT0ENABLE_LO 0x10
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#define IC_INT0ENABLE_XLO 0x14
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#define IC_INT0STATUS_LO 0x18
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#define IC_INT0STATUS_XLO 0x1c
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static struct irq_domain *digicolor_irq_domain;
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static void __exception_irq_entry digicolor_handle_irq(struct pt_regs *regs)
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{
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struct irq_domain_chip_generic *dgc = digicolor_irq_domain->gc;
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struct irq_chip_generic *gc = dgc->gc[0];
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u32 status, hwirq;
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do {
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status = irq_reg_readl(gc, IC_INT0STATUS_LO);
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if (status) {
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hwirq = ffs(status) - 1;
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} else {
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status = irq_reg_readl(gc, IC_INT0STATUS_XLO);
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if (status)
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hwirq = ffs(status) - 1 + 32;
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else
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return;
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}
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handle_domain_irq(digicolor_irq_domain, hwirq, regs);
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} while (1);
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}
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static void digicolor_set_gc(void __iomem *reg_base, unsigned irq_base,
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unsigned en_reg, unsigned ack_reg)
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{
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struct irq_chip_generic *gc;
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gc = irq_get_domain_generic_chip(digicolor_irq_domain, irq_base);
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gc->reg_base = reg_base;
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gc->chip_types[0].regs.ack = ack_reg;
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gc->chip_types[0].regs.mask = en_reg;
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gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
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gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
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gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
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}
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static int __init digicolor_of_init(struct device_node *node,
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struct device_node *parent)
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{
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static void __iomem *reg_base;
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unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
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struct regmap *ucregs;
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int ret;
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reg_base = of_iomap(node, 0);
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if (!reg_base) {
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pr_err("%s: unable to map IC registers\n", node->full_name);
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return -ENXIO;
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}
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/* disable all interrupts */
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writel(0, reg_base + IC_INT0ENABLE_LO);
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writel(0, reg_base + IC_INT0ENABLE_XLO);
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ucregs = syscon_regmap_lookup_by_phandle(node, "syscon");
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if (IS_ERR(ucregs)) {
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pr_err("%s: unable to map UC registers\n", node->full_name);
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return PTR_ERR(ucregs);
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}
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/* channel 1, regular IRQs */
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regmap_write(ucregs, UC_IRQ_CONTROL, 1);
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digicolor_irq_domain =
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irq_domain_add_linear(node, 64, &irq_generic_chip_ops, NULL);
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if (!digicolor_irq_domain) {
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pr_err("%s: unable to create IRQ domain\n", node->full_name);
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return -ENOMEM;
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}
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ret = irq_alloc_domain_generic_chips(digicolor_irq_domain, 32, 1,
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"digicolor_irq", handle_level_irq,
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clr, 0, 0);
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if (ret) {
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pr_err("%s: unable to allocate IRQ gc\n", node->full_name);
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return ret;
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}
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digicolor_set_gc(reg_base, 0, IC_INT0ENABLE_LO, IC_FLAG_CLEAR_LO);
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digicolor_set_gc(reg_base, 32, IC_INT0ENABLE_XLO, IC_FLAG_CLEAR_XLO);
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set_handle_irq(digicolor_handle_irq);
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return 0;
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}
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IRQCHIP_DECLARE(conexant_digicolor_ic, "cnxt,cx92755-ic", digicolor_of_init);
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