7f8e79cdc2
qca4019 deals with below register memory region to control the clock,
reset, etc.
- Memory to control wifi core
- gcc (outside of wifi)
- tcsr (outside of wifi)
Add new helper functions to perform read/write in above registers
spaces. Actual ioremap for above registers are done in later patch.
Struct ath10k_ahb is introduced to maintain ahb specific info and
memory this struct will be allocated in the continuation of struct
ath10k_pci (again, memory ath10k_ahb is allocated in the later patch).
Signed-off-by: Raja Mani <rmani@qti.qualcomm.com>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
123 lines
3.1 KiB
C
123 lines
3.1 KiB
C
/*
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* Copyright (c) 2016 Qualcomm Atheros, Inc. All rights reserved.
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* Copyright (c) 2015 The Linux Foundation. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <linux/module.h>
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#include "core.h"
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#include "debug.h"
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#include "pci.h"
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#include "ahb.h"
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static const struct of_device_id ath10k_ahb_of_match[] = {
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/* TODO: enable this entry once everything in place.
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* { .compatible = "qcom,ipq4019-wifi",
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* .data = (void *)ATH10K_HW_QCA4019 },
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*/
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{ }
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};
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MODULE_DEVICE_TABLE(of, ath10k_ahb_of_match);
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static inline struct ath10k_ahb *ath10k_ahb_priv(struct ath10k *ar)
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{
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return &((struct ath10k_pci *)ar->drv_priv)->ahb[0];
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}
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static void ath10k_ahb_write32(struct ath10k *ar, u32 offset, u32 value)
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{
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struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
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iowrite32(value, ar_ahb->mem + offset);
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}
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static u32 ath10k_ahb_read32(struct ath10k *ar, u32 offset)
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{
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struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
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return ioread32(ar_ahb->mem + offset);
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}
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static u32 ath10k_ahb_gcc_read32(struct ath10k *ar, u32 offset)
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{
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struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
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return ioread32(ar_ahb->gcc_mem + offset);
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}
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static void ath10k_ahb_tcsr_write32(struct ath10k *ar, u32 offset, u32 value)
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{
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struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
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iowrite32(value, ar_ahb->tcsr_mem + offset);
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}
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static u32 ath10k_ahb_tcsr_read32(struct ath10k *ar, u32 offset)
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{
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struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
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return ioread32(ar_ahb->tcsr_mem + offset);
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}
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static u32 ath10k_ahb_soc_read32(struct ath10k *ar, u32 addr)
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{
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return ath10k_ahb_read32(ar, RTC_SOC_BASE_ADDRESS + addr);
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}
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static int ath10k_ahb_get_num_banks(struct ath10k *ar)
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{
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if (ar->hw_rev == ATH10K_HW_QCA4019)
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return 1;
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ath10k_warn(ar, "unknown number of banks, assuming 1\n");
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return 1;
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}
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static int ath10k_ahb_probe(struct platform_device *pdev)
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{
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return 0;
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}
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static int ath10k_ahb_remove(struct platform_device *pdev)
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{
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return 0;
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}
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static struct platform_driver ath10k_ahb_driver = {
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.driver = {
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.name = "ath10k_ahb",
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.of_match_table = ath10k_ahb_of_match,
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},
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.probe = ath10k_ahb_probe,
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.remove = ath10k_ahb_remove,
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};
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int ath10k_ahb_init(void)
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{
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int ret;
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printk(KERN_ERR "AHB support is still work in progress\n");
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ret = platform_driver_register(&ath10k_ahb_driver);
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if (ret)
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printk(KERN_ERR "failed to register ath10k ahb driver: %d\n",
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ret);
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return ret;
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}
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void ath10k_ahb_exit(void)
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{
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platform_driver_unregister(&ath10k_ahb_driver);
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}
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