Fatemeh Darbehani 7e6472966e drm/amd/display: Change min_h_sync_width from 8 to 4 ... [Why] Some display's hsync width is lower than the minimum dcn20 is set to support right now. This will cause optc1_validate_timing to fail which eventually will result in wrong set mode. This was set to 8 as per HW team's request for no valid reason. [How] Changing min_h_sync_width to 4 will let us validate timing for preffered mode and light up the headset. This change was made to Vega 10 before for a similar issue. Signed-off-by: Fatemeh Darbehani <fatemeh.darbehani@amd.com> Reviewed-by: Joshua Aberback <Joshua.Aberback@amd.com> Acked-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2019-07-18 14:18:10 -05:00
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amdgpu_dm	drm/amd/display: add functionality to get pipe CRC source.	2019-07-18 14:18:09 -05:00
dc	drm/amd/display: Change min_h_sync_width from 8 to 4	2019-07-18 14:18:10 -05:00
include	drm/amd/display:Use Pixel clock in 100Hz units for HDMI Audio wall clock DTO	2019-07-18 14:18:09 -05:00
modules	Merge branch 'drm-next' into drm-next-5.3	2019-06-25 08:42:25 -05:00
Kconfig	drm/amd/display: Add drm_audio_component support to amdgpu_dm	2019-07-11 14:37:24 -05:00
Makefile	drm/amd/display: move clk_mgr files to right place	2019-05-31 10:39:31 -05:00
TODO	drm/amd/display: Convert remaining loggers off dc_logger	2018-07-13 14:48:42 -05:00