forked from Minki/linux
eb3d3ec567
Pull ARM updates from Russell King: - Major clean-up of the L2 cache support code. The existing mess was becoming rather unmaintainable through all the additions that others have done over time. This turns it into a much nicer structure, and implements a few performance improvements as well. - Clean up some of the CP15 control register tweaks for alignment support, moving some code and data into alignment.c - DMA properties for ARM, from Santosh and reviewed by DT people. This adds DT properties to specify bus translations we can't discover automatically, and to indicate whether devices are coherent. - Hibernation support for ARM - Make ftrace work with read-only text in modules - add suspend support for PJ4B CPUs - rework interrupt masking for undefined instruction handling, which allows us to enable interrupts earlier in the handling of these exceptions. - support for big endian page tables - fix stacktrace support to exclude stacktrace functions from the trace, and add save_stack_trace_regs() implementation so that kprobes can record stack traces. - Add support for the Cortex-A17 CPU. - Remove last vestiges of ARM710 support. - Removal of ARM "meminfo" structure, finally converting us solely to memblock to handle the early memory initialisation. * 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: (142 commits) ARM: ensure C page table setup code follows assembly code (part II) ARM: ensure C page table setup code follows assembly code ARM: consolidate last remaining open-coded alignment trap enable ARM: remove global cr_no_alignment ARM: remove CPU_CP15 conditional from alignment.c ARM: remove unused adjust_cr() function ARM: move "noalign" command line option to alignment.c ARM: provide common method to clear bits in CPU control register ARM: 8025/1: Get rid of meminfo ARM: 8060/1: mm: allow sub-architectures to override PCI I/O memory type ARM: 8066/1: correction for ARM patch 8031/2 ARM: 8049/1: ftrace/add save_stack_trace_regs() implementation ARM: 8065/1: remove last use of CONFIG_CPU_ARM710 ARM: 8062/1: Modify ldrt fixup handler to re-execute the userspace instruction ARM: 8047/1: rwsem: use asm-generic rwsem implementation ARM: l2c: trial at enabling some Cortex-A9 optimisations ARM: l2c: add warnings for stuff modifying aux_ctrl register values ARM: l2c: print a warning with L2C-310 caches if the cache size is modified ARM: l2c: remove old .set_debug method ARM: l2c: kill L2X0_AUX_CTRL_MASK before anyone else makes use of this ...
380 lines
11 KiB
C
380 lines
11 KiB
C
/*
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* linux/arch/arm/mach-realview/realview_pb11mp.c
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*
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* Copyright (C) 2008 ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/device.h>
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#include <linux/amba/bus.h>
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#include <linux/amba/pl061.h>
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#include <linux/amba/mmci.h>
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#include <linux/amba/pl022.h>
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#include <linux/io.h>
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#include <linux/irqchip/arm-gic.h>
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#include <linux/platform_data/clk-realview.h>
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#include <linux/reboot.h>
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#include <mach/hardware.h>
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#include <asm/irq.h>
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#include <asm/mach-types.h>
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#include <asm/pgtable.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/smp_twd.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/flash.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include <mach/board-pb11mp.h>
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#include <mach/irqs.h>
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#include "core.h"
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static struct map_desc realview_pb11mp_io_desc[] __initdata = {
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{
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.virtual = IO_ADDRESS(REALVIEW_SYS_BASE),
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.pfn = __phys_to_pfn(REALVIEW_SYS_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = IO_ADDRESS(REALVIEW_PB11MP_GIC_CPU_BASE),
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.pfn = __phys_to_pfn(REALVIEW_PB11MP_GIC_CPU_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = IO_ADDRESS(REALVIEW_PB11MP_GIC_DIST_BASE),
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.pfn = __phys_to_pfn(REALVIEW_PB11MP_GIC_DIST_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, { /* Maps the SCU, GIC CPU interface, TWD, GIC DIST */
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.virtual = IO_ADDRESS(REALVIEW_TC11MP_PRIV_MEM_BASE),
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.pfn = __phys_to_pfn(REALVIEW_TC11MP_PRIV_MEM_BASE),
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.length = REALVIEW_TC11MP_PRIV_MEM_SIZE,
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.type = MT_DEVICE,
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}, {
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.virtual = IO_ADDRESS(REALVIEW_SCTL_BASE),
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.pfn = __phys_to_pfn(REALVIEW_SCTL_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = IO_ADDRESS(REALVIEW_PB11MP_TIMER0_1_BASE),
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.pfn = __phys_to_pfn(REALVIEW_PB11MP_TIMER0_1_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = IO_ADDRESS(REALVIEW_PB11MP_TIMER2_3_BASE),
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.pfn = __phys_to_pfn(REALVIEW_PB11MP_TIMER2_3_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = IO_ADDRESS(REALVIEW_TC11MP_L220_BASE),
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.pfn = __phys_to_pfn(REALVIEW_TC11MP_L220_BASE),
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.length = SZ_8K,
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.type = MT_DEVICE,
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},
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#ifdef CONFIG_DEBUG_LL
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{
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.virtual = IO_ADDRESS(REALVIEW_PB11MP_UART0_BASE),
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.pfn = __phys_to_pfn(REALVIEW_PB11MP_UART0_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE,
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},
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#endif
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};
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static void __init realview_pb11mp_map_io(void)
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{
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iotable_init(realview_pb11mp_io_desc, ARRAY_SIZE(realview_pb11mp_io_desc));
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}
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static struct pl061_platform_data gpio0_plat_data = {
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.gpio_base = 0,
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};
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static struct pl061_platform_data gpio1_plat_data = {
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.gpio_base = 8,
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};
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static struct pl061_platform_data gpio2_plat_data = {
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.gpio_base = 16,
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};
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static struct pl022_ssp_controller ssp0_plat_data = {
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.bus_id = 0,
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.enable_dma = 0,
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.num_chipselect = 1,
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};
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/*
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* RealView PB11MPCore AMBA devices
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*/
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#define GPIO2_IRQ { IRQ_PB11MP_GPIO2 }
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#define GPIO3_IRQ { IRQ_PB11MP_GPIO3 }
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#define AACI_IRQ { IRQ_TC11MP_AACI }
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#define MMCI0_IRQ { IRQ_TC11MP_MMCI0A, IRQ_TC11MP_MMCI0B }
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#define KMI0_IRQ { IRQ_TC11MP_KMI0 }
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#define KMI1_IRQ { IRQ_TC11MP_KMI1 }
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#define PB11MP_SMC_IRQ { }
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#define MPMC_IRQ { }
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#define PB11MP_CLCD_IRQ { IRQ_PB11MP_CLCD }
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#define DMAC_IRQ { IRQ_PB11MP_DMAC }
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#define SCTL_IRQ { }
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#define PB11MP_WATCHDOG_IRQ { IRQ_PB11MP_WATCHDOG }
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#define PB11MP_GPIO0_IRQ { IRQ_PB11MP_GPIO0 }
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#define GPIO1_IRQ { IRQ_PB11MP_GPIO1 }
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#define PB11MP_RTC_IRQ { IRQ_TC11MP_RTC }
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#define SCI_IRQ { IRQ_PB11MP_SCI }
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#define PB11MP_UART0_IRQ { IRQ_TC11MP_UART0 }
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#define PB11MP_UART1_IRQ { IRQ_TC11MP_UART1 }
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#define PB11MP_UART2_IRQ { IRQ_PB11MP_UART2 }
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#define PB11MP_UART3_IRQ { IRQ_PB11MP_UART3 }
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#define PB11MP_SSP_IRQ { IRQ_PB11MP_SSP }
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/* FPGA Primecells */
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APB_DEVICE(aaci, "fpga:aaci", AACI, NULL);
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APB_DEVICE(mmc0, "fpga:mmc0", MMCI0, &realview_mmc0_plat_data);
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APB_DEVICE(kmi0, "fpga:kmi0", KMI0, NULL);
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APB_DEVICE(kmi1, "fpga:kmi1", KMI1, NULL);
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APB_DEVICE(uart3, "fpga:uart3", PB11MP_UART3, NULL);
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/* DevChip Primecells */
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AHB_DEVICE(smc, "dev:smc", PB11MP_SMC, NULL);
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AHB_DEVICE(sctl, "dev:sctl", SCTL, NULL);
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APB_DEVICE(wdog, "dev:wdog", PB11MP_WATCHDOG, NULL);
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APB_DEVICE(gpio0, "dev:gpio0", PB11MP_GPIO0, &gpio0_plat_data);
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APB_DEVICE(gpio1, "dev:gpio1", GPIO1, &gpio1_plat_data);
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APB_DEVICE(gpio2, "dev:gpio2", GPIO2, &gpio2_plat_data);
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APB_DEVICE(rtc, "dev:rtc", PB11MP_RTC, NULL);
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APB_DEVICE(sci0, "dev:sci0", SCI, NULL);
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APB_DEVICE(uart0, "dev:uart0", PB11MP_UART0, NULL);
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APB_DEVICE(uart1, "dev:uart1", PB11MP_UART1, NULL);
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APB_DEVICE(uart2, "dev:uart2", PB11MP_UART2, NULL);
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APB_DEVICE(ssp0, "dev:ssp0", PB11MP_SSP, &ssp0_plat_data);
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/* Primecells on the NEC ISSP chip */
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AHB_DEVICE(clcd, "issp:clcd", PB11MP_CLCD, &clcd_plat_data);
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AHB_DEVICE(dmac, "issp:dmac", DMAC, NULL);
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static struct amba_device *amba_devs[] __initdata = {
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&dmac_device,
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&uart0_device,
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&uart1_device,
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&uart2_device,
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&uart3_device,
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&smc_device,
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&clcd_device,
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&sctl_device,
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&wdog_device,
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&gpio0_device,
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&gpio1_device,
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&gpio2_device,
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&rtc_device,
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&sci0_device,
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&ssp0_device,
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&aaci_device,
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&mmc0_device,
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&kmi0_device,
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&kmi1_device,
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};
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/*
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* RealView PB11MPCore platform devices
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*/
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static struct resource realview_pb11mp_flash_resource[] = {
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[0] = {
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.start = REALVIEW_PB11MP_FLASH0_BASE,
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.end = REALVIEW_PB11MP_FLASH0_BASE + REALVIEW_PB11MP_FLASH0_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = REALVIEW_PB11MP_FLASH1_BASE,
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.end = REALVIEW_PB11MP_FLASH1_BASE + REALVIEW_PB11MP_FLASH1_SIZE - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct resource realview_pb11mp_smsc911x_resources[] = {
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[0] = {
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.start = REALVIEW_PB11MP_ETH_BASE,
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.end = REALVIEW_PB11MP_ETH_BASE + SZ_64K - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_TC11MP_ETH,
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.end = IRQ_TC11MP_ETH,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct resource realview_pb11mp_isp1761_resources[] = {
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[0] = {
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.start = REALVIEW_PB11MP_USB_BASE,
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.end = REALVIEW_PB11MP_USB_BASE + SZ_128K - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = IRQ_TC11MP_USB,
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.end = IRQ_TC11MP_USB,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct resource pmu_resources[] = {
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[0] = {
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.start = IRQ_TC11MP_PMU_CPU0,
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.end = IRQ_TC11MP_PMU_CPU0,
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.flags = IORESOURCE_IRQ,
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},
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[1] = {
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.start = IRQ_TC11MP_PMU_CPU1,
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.end = IRQ_TC11MP_PMU_CPU1,
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.flags = IORESOURCE_IRQ,
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},
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[2] = {
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.start = IRQ_TC11MP_PMU_CPU2,
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.end = IRQ_TC11MP_PMU_CPU2,
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.flags = IORESOURCE_IRQ,
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},
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[3] = {
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.start = IRQ_TC11MP_PMU_CPU3,
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.end = IRQ_TC11MP_PMU_CPU3,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device pmu_device = {
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.name = "arm-pmu",
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.id = -1,
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.num_resources = ARRAY_SIZE(pmu_resources),
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.resource = pmu_resources,
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};
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static void __init gic_init_irq(void)
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{
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unsigned int pldctrl;
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/* new irq mode with no DCC */
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writel(0x0000a05f, __io_address(REALVIEW_SYS_LOCK));
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pldctrl = readl(__io_address(REALVIEW_SYS_BASE) + REALVIEW_PB11MP_SYS_PLD_CTRL1);
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pldctrl |= 2 << 22;
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writel(pldctrl, __io_address(REALVIEW_SYS_BASE) + REALVIEW_PB11MP_SYS_PLD_CTRL1);
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writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
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/* ARM11MPCore test chip GIC, primary */
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gic_init(0, 29, __io_address(REALVIEW_TC11MP_GIC_DIST_BASE),
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__io_address(REALVIEW_TC11MP_GIC_CPU_BASE));
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/* board GIC, secondary */
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gic_init(1, IRQ_PB11MP_GIC_START,
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__io_address(REALVIEW_PB11MP_GIC_DIST_BASE),
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__io_address(REALVIEW_PB11MP_GIC_CPU_BASE));
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gic_cascade_irq(1, IRQ_TC11MP_PB_IRQ1);
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}
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#ifdef CONFIG_HAVE_ARM_TWD
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static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
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REALVIEW_TC11MP_TWD_BASE,
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IRQ_LOCALTIMER);
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static void __init realview_pb11mp_twd_init(void)
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{
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int err = twd_local_timer_register(&twd_local_timer);
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if (err)
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pr_err("twd_local_timer_register failed %d\n", err);
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}
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#else
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#define realview_pb11mp_twd_init() do {} while(0)
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#endif
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static void __init realview_pb11mp_timer_init(void)
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{
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timer0_va_base = __io_address(REALVIEW_PB11MP_TIMER0_1_BASE);
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timer1_va_base = __io_address(REALVIEW_PB11MP_TIMER0_1_BASE) + 0x20;
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timer2_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE);
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timer3_va_base = __io_address(REALVIEW_PB11MP_TIMER2_3_BASE) + 0x20;
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realview_clk_init(__io_address(REALVIEW_SYS_BASE), false);
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realview_timer_init(IRQ_TC11MP_TIMER0_1);
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realview_pb11mp_twd_init();
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}
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static void realview_pb11mp_restart(enum reboot_mode mode, const char *cmd)
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{
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void __iomem *reset_ctrl = __io_address(REALVIEW_SYS_RESETCTL);
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void __iomem *lock_ctrl = __io_address(REALVIEW_SYS_LOCK);
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/*
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* To reset, we hit the on-board reset register
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* in the system FPGA
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*/
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__raw_writel(REALVIEW_SYS_LOCK_VAL, lock_ctrl);
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__raw_writel(0x0000, reset_ctrl);
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__raw_writel(0x0004, reset_ctrl);
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dsb();
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}
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static void __init realview_pb11mp_init(void)
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{
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int i;
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#ifdef CONFIG_CACHE_L2X0
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/*
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* The PL220 needs to be manually configured as the hardware
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* doesn't report the correct sizes.
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* 1MB (128KB/way), 8-way associativity, event monitor and
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* parity enabled, ignore share bit, no force write allocate
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* Bits: .... ...0 0111 1001 0000 .... .... ....
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*/
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l2x0_init(__io_address(REALVIEW_TC11MP_L220_BASE), 0x00790000, 0xfe000fff);
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#endif
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realview_flash_register(realview_pb11mp_flash_resource,
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ARRAY_SIZE(realview_pb11mp_flash_resource));
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realview_eth_register(NULL, realview_pb11mp_smsc911x_resources);
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platform_device_register(&realview_i2c_device);
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platform_device_register(&realview_cf_device);
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platform_device_register(&realview_leds_device);
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realview_usb_register(realview_pb11mp_isp1761_resources);
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platform_device_register(&pmu_device);
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for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
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struct amba_device *d = amba_devs[i];
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amba_device_register(d, &iomem_resource);
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}
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}
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MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore")
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/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
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.atag_offset = 0x100,
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.smp = smp_ops(realview_smp_ops),
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.fixup = realview_fixup,
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.map_io = realview_pb11mp_map_io,
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.init_early = realview_init_early,
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.init_irq = gic_init_irq,
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.init_time = realview_pb11mp_timer_init,
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.init_machine = realview_pb11mp_init,
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#ifdef CONFIG_ZONE_DMA
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.dma_zone_size = SZ_256M,
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#endif
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.restart = realview_pb11mp_restart,
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MACHINE_END
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