Will Deacon 40c390c768 ARM: perf: don't pretend to support counting of L1I writes ...

ARM has a harvard cache architecture and cannot write directly to the
I-side.

This patch removes the L1I write events from the cache map (which
previously returned *read* events in many cases).

Reported-by: Mike Williams <michael.williams@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>

2013-01-16 12:01:59 +00:00

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