forked from Minki/linux
3c726f8dee
Adds a new CONFIG_PPC_64K_PAGES which, when enabled, changes the kernel base page size to 64K. The resulting kernel still boots on any hardware. On current machines with 4K pages support only, the kernel will maintain 16 "subpages" for each 64K page transparently. Note that while real 64K capable HW has been tested, the current patch will not enable it yet as such hardware is not released yet, and I'm still verifying with the firmware architects the proper to get the information from the newer hypervisors. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
412 lines
11 KiB
C
412 lines
11 KiB
C
/*
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* Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
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*/
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#ifndef _ASM_POWERPC_SYSTEM_H
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#define _ASM_POWERPC_SYSTEM_H
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#include <linux/config.h>
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#include <linux/kernel.h>
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#include <asm/hw_irq.h>
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#include <asm/ppc_asm.h>
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#include <asm/atomic.h>
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/*
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* Memory barrier.
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* The sync instruction guarantees that all memory accesses initiated
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* by this processor have been performed (with respect to all other
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* mechanisms that access memory). The eieio instruction is a barrier
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* providing an ordering (separately) for (a) cacheable stores and (b)
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* loads and stores to non-cacheable memory (e.g. I/O devices).
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*
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* mb() prevents loads and stores being reordered across this point.
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* rmb() prevents loads being reordered across this point.
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* wmb() prevents stores being reordered across this point.
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* read_barrier_depends() prevents data-dependent loads being reordered
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* across this point (nop on PPC).
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*
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* We have to use the sync instructions for mb(), since lwsync doesn't
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* order loads with respect to previous stores. Lwsync is fine for
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* rmb(), though. Note that lwsync is interpreted as sync by
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* 32-bit and older 64-bit CPUs.
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*
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* For wmb(), we use sync since wmb is used in drivers to order
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* stores to system memory with respect to writes to the device.
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* However, smp_wmb() can be a lighter-weight eieio barrier on
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* SMP since it is only used to order updates to system memory.
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*/
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#define mb() __asm__ __volatile__ ("sync" : : : "memory")
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#define rmb() __asm__ __volatile__ ("lwsync" : : : "memory")
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#define wmb() __asm__ __volatile__ ("sync" : : : "memory")
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#define read_barrier_depends() do { } while(0)
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#define set_mb(var, value) do { var = value; mb(); } while (0)
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#define set_wmb(var, value) do { var = value; wmb(); } while (0)
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#ifdef CONFIG_SMP
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#define smp_mb() mb()
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#define smp_rmb() rmb()
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#define smp_wmb() __asm__ __volatile__ ("eieio" : : : "memory")
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#define smp_read_barrier_depends() read_barrier_depends()
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#else
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#define smp_read_barrier_depends() do { } while(0)
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#endif /* CONFIG_SMP */
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#ifdef __KERNEL__
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struct task_struct;
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struct pt_regs;
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#ifdef CONFIG_DEBUGGER
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extern int (*__debugger)(struct pt_regs *regs);
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extern int (*__debugger_ipi)(struct pt_regs *regs);
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extern int (*__debugger_bpt)(struct pt_regs *regs);
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extern int (*__debugger_sstep)(struct pt_regs *regs);
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extern int (*__debugger_iabr_match)(struct pt_regs *regs);
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extern int (*__debugger_dabr_match)(struct pt_regs *regs);
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extern int (*__debugger_fault_handler)(struct pt_regs *regs);
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#define DEBUGGER_BOILERPLATE(__NAME) \
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static inline int __NAME(struct pt_regs *regs) \
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{ \
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if (unlikely(__ ## __NAME)) \
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return __ ## __NAME(regs); \
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return 0; \
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}
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DEBUGGER_BOILERPLATE(debugger)
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DEBUGGER_BOILERPLATE(debugger_ipi)
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DEBUGGER_BOILERPLATE(debugger_bpt)
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DEBUGGER_BOILERPLATE(debugger_sstep)
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DEBUGGER_BOILERPLATE(debugger_iabr_match)
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DEBUGGER_BOILERPLATE(debugger_dabr_match)
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DEBUGGER_BOILERPLATE(debugger_fault_handler)
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#ifdef CONFIG_XMON
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extern void xmon_init(int enable);
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#endif
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#else
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static inline int debugger(struct pt_regs *regs) { return 0; }
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static inline int debugger_ipi(struct pt_regs *regs) { return 0; }
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static inline int debugger_bpt(struct pt_regs *regs) { return 0; }
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static inline int debugger_sstep(struct pt_regs *regs) { return 0; }
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static inline int debugger_iabr_match(struct pt_regs *regs) { return 0; }
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static inline int debugger_dabr_match(struct pt_regs *regs) { return 0; }
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static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; }
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#endif
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extern int set_dabr(unsigned long dabr);
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extern void print_backtrace(unsigned long *);
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extern void show_regs(struct pt_regs * regs);
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extern void flush_instruction_cache(void);
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extern void hard_reset_now(void);
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extern void poweroff_now(void);
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#ifdef CONFIG_6xx
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extern long _get_L2CR(void);
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extern long _get_L3CR(void);
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extern void _set_L2CR(unsigned long);
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extern void _set_L3CR(unsigned long);
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#else
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#define _get_L2CR() 0L
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#define _get_L3CR() 0L
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#define _set_L2CR(val) do { } while(0)
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#define _set_L3CR(val) do { } while(0)
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#endif
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extern void via_cuda_init(void);
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extern void read_rtc_time(void);
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extern void pmac_find_display(void);
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extern void giveup_fpu(struct task_struct *);
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extern void disable_kernel_fp(void);
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extern void enable_kernel_fp(void);
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extern void flush_fp_to_thread(struct task_struct *);
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extern void enable_kernel_altivec(void);
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extern void giveup_altivec(struct task_struct *);
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extern void load_up_altivec(struct task_struct *);
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extern int emulate_altivec(struct pt_regs *);
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extern void giveup_spe(struct task_struct *);
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extern void load_up_spe(struct task_struct *);
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extern int fix_alignment(struct pt_regs *);
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extern void cvt_fd(float *from, double *to, struct thread_struct *thread);
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extern void cvt_df(double *from, float *to, struct thread_struct *thread);
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#ifdef CONFIG_ALTIVEC
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extern void flush_altivec_to_thread(struct task_struct *);
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#else
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static inline void flush_altivec_to_thread(struct task_struct *t)
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{
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}
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#endif
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#ifdef CONFIG_SPE
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extern void flush_spe_to_thread(struct task_struct *);
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#else
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static inline void flush_spe_to_thread(struct task_struct *t)
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{
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}
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#endif
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extern int call_rtas(const char *, int, int, unsigned long *, ...);
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extern void cacheable_memzero(void *p, unsigned int nb);
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extern void *cacheable_memcpy(void *, const void *, unsigned int);
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extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
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extern void bad_page_fault(struct pt_regs *, unsigned long, int);
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extern int die(const char *, struct pt_regs *, long);
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extern void _exception(int, struct pt_regs *, int, unsigned long);
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#ifdef CONFIG_BOOKE_WDT
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extern u32 booke_wdt_enabled;
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extern u32 booke_wdt_period;
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#endif /* CONFIG_BOOKE_WDT */
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/* EBCDIC -> ASCII conversion for [0-9A-Z] on iSeries */
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extern unsigned char e2a(unsigned char);
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struct device_node;
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extern void note_scsi_host(struct device_node *, void *);
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extern struct task_struct *__switch_to(struct task_struct *,
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struct task_struct *);
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#define switch_to(prev, next, last) ((last) = __switch_to((prev), (next)))
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struct thread_struct;
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extern struct task_struct *_switch(struct thread_struct *prev,
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struct thread_struct *next);
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extern unsigned int rtas_data;
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extern int mem_init_done; /* set on boot once kmalloc can be called */
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extern unsigned long memory_limit;
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extern int powersave_nap; /* set if nap mode can be used in idle loop */
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/*
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* Atomic exchange
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*
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* Changes the memory location '*ptr' to be val and returns
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* the previous value stored there.
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*/
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static __inline__ unsigned long
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__xchg_u32(volatile void *p, unsigned long val)
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{
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unsigned long prev;
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__asm__ __volatile__(
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EIEIO_ON_SMP
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"1: lwarx %0,0,%2 \n"
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PPC405_ERR77(0,%2)
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" stwcx. %3,0,%2 \n\
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bne- 1b"
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ISYNC_ON_SMP
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: "=&r" (prev), "=m" (*(volatile unsigned int *)p)
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: "r" (p), "r" (val), "m" (*(volatile unsigned int *)p)
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: "cc", "memory");
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return prev;
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}
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#ifdef CONFIG_PPC64
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static __inline__ unsigned long
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__xchg_u64(volatile void *p, unsigned long val)
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{
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unsigned long prev;
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__asm__ __volatile__(
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EIEIO_ON_SMP
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"1: ldarx %0,0,%2 \n"
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PPC405_ERR77(0,%2)
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" stdcx. %3,0,%2 \n\
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bne- 1b"
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ISYNC_ON_SMP
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: "=&r" (prev), "=m" (*(volatile unsigned long *)p)
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: "r" (p), "r" (val), "m" (*(volatile unsigned long *)p)
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: "cc", "memory");
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return prev;
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}
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#endif
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/*
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* This function doesn't exist, so you'll get a linker error
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* if something tries to do an invalid xchg().
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*/
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extern void __xchg_called_with_bad_pointer(void);
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static __inline__ unsigned long
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__xchg(volatile void *ptr, unsigned long x, unsigned int size)
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{
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switch (size) {
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case 4:
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return __xchg_u32(ptr, x);
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#ifdef CONFIG_PPC64
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case 8:
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return __xchg_u64(ptr, x);
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#endif
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}
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__xchg_called_with_bad_pointer();
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return x;
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}
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#define xchg(ptr,x) \
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({ \
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__typeof__(*(ptr)) _x_ = (x); \
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(__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \
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})
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#define tas(ptr) (xchg((ptr),1))
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/*
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* Compare and exchange - if *p == old, set it to new,
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* and return the old value of *p.
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*/
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#define __HAVE_ARCH_CMPXCHG 1
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static __inline__ unsigned long
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__cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new)
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{
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unsigned int prev;
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__asm__ __volatile__ (
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EIEIO_ON_SMP
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"1: lwarx %0,0,%2 # __cmpxchg_u32\n\
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cmpw 0,%0,%3\n\
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bne- 2f\n"
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PPC405_ERR77(0,%2)
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" stwcx. %4,0,%2\n\
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bne- 1b"
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ISYNC_ON_SMP
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"\n\
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2:"
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: "=&r" (prev), "=m" (*p)
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: "r" (p), "r" (old), "r" (new), "m" (*p)
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: "cc", "memory");
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return prev;
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}
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#ifdef CONFIG_PPC64
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static __inline__ unsigned long
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__cmpxchg_u64(volatile unsigned long *p, unsigned long old, unsigned long new)
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{
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unsigned long prev;
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__asm__ __volatile__ (
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EIEIO_ON_SMP
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"1: ldarx %0,0,%2 # __cmpxchg_u64\n\
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cmpd 0,%0,%3\n\
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bne- 2f\n\
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stdcx. %4,0,%2\n\
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bne- 1b"
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ISYNC_ON_SMP
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"\n\
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2:"
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: "=&r" (prev), "=m" (*p)
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: "r" (p), "r" (old), "r" (new), "m" (*p)
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: "cc", "memory");
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return prev;
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}
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#endif
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/* This function doesn't exist, so you'll get a linker error
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if something tries to do an invalid cmpxchg(). */
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extern void __cmpxchg_called_with_bad_pointer(void);
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static __inline__ unsigned long
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__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new,
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unsigned int size)
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{
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switch (size) {
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case 4:
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return __cmpxchg_u32(ptr, old, new);
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#ifdef CONFIG_PPC64
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case 8:
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return __cmpxchg_u64(ptr, old, new);
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#endif
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}
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__cmpxchg_called_with_bad_pointer();
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return old;
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}
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#define cmpxchg(ptr,o,n) \
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({ \
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__typeof__(*(ptr)) _o_ = (o); \
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__typeof__(*(ptr)) _n_ = (n); \
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(__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
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(unsigned long)_n_, sizeof(*(ptr))); \
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})
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#ifdef CONFIG_PPC64
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/*
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* We handle most unaligned accesses in hardware. On the other hand
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* unaligned DMA can be very expensive on some ppc64 IO chips (it does
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* powers of 2 writes until it reaches sufficient alignment).
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*
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* Based on this we disable the IP header alignment in network drivers.
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*/
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#define NET_IP_ALIGN 0
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#endif
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#define arch_align_stack(x) (x)
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/* Used in very early kernel initialization. */
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extern unsigned long reloc_offset(void);
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extern unsigned long add_reloc_offset(unsigned long);
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extern void reloc_got2(unsigned long);
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#define PTRRELOC(x) ((typeof(x)) add_reloc_offset((unsigned long)(x)))
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static inline void create_instruction(unsigned long addr, unsigned int instr)
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{
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unsigned int *p;
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p = (unsigned int *)addr;
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*p = instr;
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asm ("dcbst 0, %0; sync; icbi 0,%0; sync; isync" : : "r" (p));
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}
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/* Flags for create_branch:
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* "b" == create_branch(addr, target, 0);
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* "ba" == create_branch(addr, target, BRANCH_ABSOLUTE);
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* "bl" == create_branch(addr, target, BRANCH_SET_LINK);
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* "bla" == create_branch(addr, target, BRANCH_ABSOLUTE | BRANCH_SET_LINK);
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*/
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#define BRANCH_SET_LINK 0x1
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#define BRANCH_ABSOLUTE 0x2
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static inline void create_branch(unsigned long addr,
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unsigned long target, int flags)
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{
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unsigned int instruction;
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if (! (flags & BRANCH_ABSOLUTE))
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target = target - addr;
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/* Mask out the flags and target, so they don't step on each other. */
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instruction = 0x48000000 | (flags & 0x3) | (target & 0x03FFFFFC);
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create_instruction(addr, instruction);
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}
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static inline void create_function_call(unsigned long addr, void * func)
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{
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unsigned long func_addr;
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#ifdef CONFIG_PPC64
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/*
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* On PPC64 the function pointer actually points to the function's
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* descriptor. The first entry in the descriptor is the address
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* of the function text.
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*/
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func_addr = *(unsigned long *)func;
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#else
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func_addr = (unsigned long)func;
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#endif
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create_branch(addr, func_addr, BRANCH_SET_LINK);
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}
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_SYSTEM_H */
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