8b83369ddc
Pull RISC-V updates from Palmer Dabbelt:
"A handful of new RISC-V related patches for this merge window:
- A check to ensure drivers are properly using uaccess. This isn't
manifesting with any of the drivers I'm currently using, but may
catch errors in new drivers.
- Some preliminary support for the FU740, along with the HiFive
Unleashed it will appear on.
- NUMA support for RISC-V, which involves making the arm64 code
generic.
- Support for kasan on the vmalloc region.
- A handful of new drivers for the Kendryte K210, along with the DT
plumbing required to boot on a handful of K210-based boards.
- Support for allocating ASIDs.
- Preliminary support for kernels larger than 128MiB.
- Various other improvements to our KASAN support, including the
utilization of huge pages when allocating the KASAN regions.
We may have already found a bug with the KASAN_VMALLOC code, but it's
passing my tests. There's a fix in the works, but that will probably
miss the merge window.
* tag 'riscv-for-linus-5.12-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (75 commits)
riscv: Improve kasan population by using hugepages when possible
riscv: Improve kasan population function
riscv: Use KASAN_SHADOW_INIT define for kasan memory initialization
riscv: Improve kasan definitions
riscv: Get rid of MAX_EARLY_MAPPING_SIZE
soc: canaan: Sort the Makefile alphabetically
riscv: Disable KSAN_SANITIZE for vDSO
riscv: Remove unnecessary declaration
riscv: Add Canaan Kendryte K210 SD card defconfig
riscv: Update Canaan Kendryte K210 defconfig
riscv: Add Kendryte KD233 board device tree
riscv: Add SiPeed MAIXDUINO board device tree
riscv: Add SiPeed MAIX GO board device tree
riscv: Add SiPeed MAIX DOCK board device tree
riscv: Add SiPeed MAIX BiT board device tree
riscv: Update Canaan Kendryte K210 device tree
dt-bindings: add resets property to dw-apb-timer
dt-bindings: fix sifive gpio properties
dt-bindings: update sifive uart compatible string
dt-bindings: update sifive clint compatible string
...
46 lines
1.4 KiB
C
46 lines
1.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2019 SiFive
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*/
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#ifndef _ASM_RISCV_SET_MEMORY_H
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#define _ASM_RISCV_SET_MEMORY_H
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#ifndef __ASSEMBLY__
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/*
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* Functions to change memory attributes.
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*/
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#ifdef CONFIG_MMU
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int set_memory_ro(unsigned long addr, int numpages);
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int set_memory_rw(unsigned long addr, int numpages);
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int set_memory_x(unsigned long addr, int numpages);
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int set_memory_nx(unsigned long addr, int numpages);
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int set_memory_rw_nx(unsigned long addr, int numpages);
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void protect_kernel_text_data(void);
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#else
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static inline int set_memory_ro(unsigned long addr, int numpages) { return 0; }
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static inline int set_memory_rw(unsigned long addr, int numpages) { return 0; }
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static inline int set_memory_x(unsigned long addr, int numpages) { return 0; }
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static inline int set_memory_nx(unsigned long addr, int numpages) { return 0; }
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static inline void protect_kernel_text_data(void) {}
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static inline int set_memory_rw_nx(unsigned long addr, int numpages) { return 0; }
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#endif
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int set_direct_map_invalid_noflush(struct page *page);
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int set_direct_map_default_noflush(struct page *page);
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bool kernel_page_present(struct page *page);
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#endif /* __ASSEMBLY__ */
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#ifdef CONFIG_STRICT_KERNEL_RWX
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#ifdef CONFIG_64BIT
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#define SECTION_ALIGN (1 << 21)
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#else
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#define SECTION_ALIGN (1 << 22)
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#endif
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#else /* !CONFIG_STRICT_KERNEL_RWX */
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#define SECTION_ALIGN L1_CACHE_BYTES
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#endif /* CONFIG_STRICT_KERNEL_RWX */
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#endif /* _ASM_RISCV_SET_MEMORY_H */
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