7672691a08
POWER9 processors up to and including "Nimbus" v2.2 have hardware bugs relating to transactional memory and thread reconfiguration. One of these bugs has a workaround which is to get the core into SMT4 state temporarily. This workaround is only needed when running bare-metal. This patch provides a function which gets the core into SMT4 mode by preventing threads from going to a stop state, and waking up those which are already in a stop state. Once at least 3 threads are not in a stop state, the core will be in SMT4 and we can continue. To do this, we add a "dont_stop" flag to the paca to tell the thread not to go into a stop state. If this flag is set, power9_idle_stop() just returns immediately with a return value of 0. The pnv_power9_force_smt4_catch() function does the following: 1. Set the dont_stop flag for each thread in the core, except ourselves (in fact we use an atomic_inc() in case more than one thread is calling this function concurrently). 2. See how many threads are awake, indicated by their requested_psscr field in the paca being 0. If this is at least 3, skip to step 5. 3. Send a doorbell interrupt to each thread that was seen as being in a stop state in step 2. 4. Until at least 3 threads are awake, scan the threads to which we sent a doorbell interrupt and check if they are awake now. This relies on the following properties: - Once dont_stop is non-zero, requested_psccr can't go from zero to non-zero, except transiently (and without the thread doing stop). - requested_psscr being zero guarantees that the thread isn't in a state-losing stop state where thread reconfiguration could occur. - Doing stop with a PSSCR value of 0 won't be a state-losing stop and thus won't allow thread reconfiguration. - Once threads_per_core/2 + 1 (i.e. 3) threads are awake, the core must be in SMT4 mode, since SMT modes are powers of 2. This does add a sync to power9_idle_stop(), which is necessary to provide the correct ordering between setting requested_psscr and checking dont_stop. The overhead of the sync should be unnoticeable compared to the latency of going into and out of a stop state. Because some objected to incurring this extra latency on systems where the XER[SO] bug is not relevant, I have put the test in power9_idle_stop inside a feature section. This means that pnv_power9_force_smt4_catch() WILL NOT WORK correctly on systems without the CPU_FTR_P9_TM_XER_SO_BUG feature bit set, and will probably hang the system. In order to cater for uses where the caller has an operation that has to be done while the core is in SMT4, the core continues to be kept in SMT4 after pnv_power9_force_smt4_catch() function returns, until the pnv_power9_force_smt4_release() function is called. It undoes the effect of step 1 above and allows the other threads to go into a stop state. Signed-off-by: Paul Mackerras <paulus@ozlabs.org> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
265 lines
8.0 KiB
C
265 lines
8.0 KiB
C
/*
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* This control block defines the PACA which defines the processor
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* specific data for each logical processor on the system.
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* There are some pointers defined that are utilized by PLIC.
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*
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* C 2001 PPC 64 Team, IBM Corp
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef _ASM_POWERPC_PACA_H
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#define _ASM_POWERPC_PACA_H
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#ifdef __KERNEL__
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#ifdef CONFIG_PPC64
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#include <linux/string.h>
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#include <asm/types.h>
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#include <asm/lppaca.h>
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#include <asm/mmu.h>
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#include <asm/page.h>
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#ifdef CONFIG_PPC_BOOK3E
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#include <asm/exception-64e.h>
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#else
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#include <asm/exception-64s.h>
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#endif
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#ifdef CONFIG_KVM_BOOK3S_64_HANDLER
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#include <asm/kvm_book3s_asm.h>
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#endif
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#include <asm/accounting.h>
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#include <asm/hmi.h>
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#include <asm/cpuidle.h>
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#include <asm/atomic.h>
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register struct paca_struct *local_paca asm("r13");
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#if defined(CONFIG_DEBUG_PREEMPT) && defined(CONFIG_SMP)
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extern unsigned int debug_smp_processor_id(void); /* from linux/smp.h */
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/*
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* Add standard checks that preemption cannot occur when using get_paca():
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* otherwise the paca_struct it points to may be the wrong one just after.
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*/
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#define get_paca() ((void) debug_smp_processor_id(), local_paca)
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#else
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#define get_paca() local_paca
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#endif
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#define get_lppaca() (get_paca()->lppaca_ptr)
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#define get_slb_shadow() (get_paca()->slb_shadow_ptr)
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struct task_struct;
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/*
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* Defines the layout of the paca.
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*
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* This structure is not directly accessed by firmware or the service
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* processor.
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*/
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struct paca_struct {
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#ifdef CONFIG_PPC_BOOK3S
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/*
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* Because hw_cpu_id, unlike other paca fields, is accessed
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* routinely from other CPUs (from the IRQ code), we stick to
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* read-only (after boot) fields in the first cacheline to
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* avoid cacheline bouncing.
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*/
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struct lppaca *lppaca_ptr; /* Pointer to LpPaca for PLIC */
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#endif /* CONFIG_PPC_BOOK3S */
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/*
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* MAGIC: the spinlock functions in arch/powerpc/lib/locks.c
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* load lock_token and paca_index with a single lwz
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* instruction. They must travel together and be properly
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* aligned.
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*/
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#ifdef __BIG_ENDIAN__
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u16 lock_token; /* Constant 0x8000, used in locks */
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u16 paca_index; /* Logical processor number */
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#else
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u16 paca_index; /* Logical processor number */
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u16 lock_token; /* Constant 0x8000, used in locks */
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#endif
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u64 kernel_toc; /* Kernel TOC address */
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u64 kernelbase; /* Base address of kernel */
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u64 kernel_msr; /* MSR while running in kernel */
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void *emergency_sp; /* pointer to emergency stack */
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u64 data_offset; /* per cpu data offset */
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s16 hw_cpu_id; /* Physical processor number */
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u8 cpu_start; /* At startup, processor spins until */
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/* this becomes non-zero. */
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u8 kexec_state; /* set when kexec down has irqs off */
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#ifdef CONFIG_PPC_BOOK3S_64
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struct slb_shadow *slb_shadow_ptr;
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struct dtl_entry *dispatch_log;
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struct dtl_entry *dispatch_log_end;
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#endif
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u64 dscr_default; /* per-CPU default DSCR */
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#ifdef CONFIG_PPC_BOOK3S_64
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/*
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* Now, starting in cacheline 2, the exception save areas
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*/
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/* used for most interrupts/exceptions */
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u64 exgen[EX_SIZE] __attribute__((aligned(0x80)));
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u64 exslb[EX_SIZE]; /* used for SLB/segment table misses
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* on the linear mapping */
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/* SLB related definitions */
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u16 vmalloc_sllp;
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u16 slb_cache_ptr;
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u32 slb_cache[SLB_CACHE_ENTRIES];
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#endif /* CONFIG_PPC_BOOK3S_64 */
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#ifdef CONFIG_PPC_BOOK3E
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u64 exgen[8] __aligned(0x40);
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/* Keep pgd in the same cacheline as the start of extlb */
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pgd_t *pgd __aligned(0x40); /* Current PGD */
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pgd_t *kernel_pgd; /* Kernel PGD */
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/* Shared by all threads of a core -- points to tcd of first thread */
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struct tlb_core_data *tcd_ptr;
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/*
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* We can have up to 3 levels of reentrancy in the TLB miss handler,
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* in each of four exception levels (normal, crit, mcheck, debug).
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*/
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u64 extlb[12][EX_TLB_SIZE / sizeof(u64)];
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u64 exmc[8]; /* used for machine checks */
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u64 excrit[8]; /* used for crit interrupts */
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u64 exdbg[8]; /* used for debug interrupts */
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/* Kernel stack pointers for use by special exceptions */
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void *mc_kstack;
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void *crit_kstack;
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void *dbg_kstack;
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struct tlb_core_data tcd;
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#endif /* CONFIG_PPC_BOOK3E */
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#ifdef CONFIG_PPC_BOOK3S
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mm_context_id_t mm_ctx_id;
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#ifdef CONFIG_PPC_MM_SLICES
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u64 mm_ctx_low_slices_psize;
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unsigned char mm_ctx_high_slices_psize[SLICE_ARRAY_SIZE];
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unsigned long mm_ctx_slb_addr_limit;
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#else
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u16 mm_ctx_user_psize;
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u16 mm_ctx_sllp;
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#endif
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#endif
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/*
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* then miscellaneous read-write fields
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*/
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struct task_struct *__current; /* Pointer to current */
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u64 kstack; /* Saved Kernel stack addr */
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u64 stab_rr; /* stab/slb round-robin counter */
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u64 saved_r1; /* r1 save for RTAS calls or PM */
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u64 saved_msr; /* MSR saved here by enter_rtas */
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u16 trap_save; /* Used when bad stack is encountered */
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u8 irq_soft_mask; /* mask for irq soft masking */
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u8 irq_happened; /* irq happened while soft-disabled */
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u8 io_sync; /* writel() needs spin_unlock sync */
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u8 irq_work_pending; /* IRQ_WORK interrupt while soft-disable */
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u8 nap_state_lost; /* NV GPR values lost in power7_idle */
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u64 sprg_vdso; /* Saved user-visible sprg */
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#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
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u64 tm_scratch; /* TM scratch area for reclaim */
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#endif
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#ifdef CONFIG_PPC_POWERNV
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/* Per-core mask tracking idle threads and a lock bit-[L][TTTTTTTT] */
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u32 *core_idle_state_ptr;
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u8 thread_idle_state; /* PNV_THREAD_RUNNING/NAP/SLEEP */
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/* Mask to indicate thread id in core */
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u8 thread_mask;
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/* Mask to denote subcore sibling threads */
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u8 subcore_sibling_mask;
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/* Flag to request this thread not to stop */
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atomic_t dont_stop;
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/*
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* Pointer to an array which contains pointer
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* to the sibling threads' paca.
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*/
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struct paca_struct **thread_sibling_pacas;
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/* The PSSCR value that the kernel requested before going to stop */
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u64 requested_psscr;
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/*
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* Save area for additional SPRs that need to be
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* saved/restored during cpuidle stop.
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*/
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struct stop_sprs stop_sprs;
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#endif
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#ifdef CONFIG_PPC_BOOK3S_64
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/* Non-maskable exceptions that are not performance critical */
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u64 exnmi[EX_SIZE]; /* used for system reset (nmi) */
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u64 exmc[EX_SIZE]; /* used for machine checks */
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#endif
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#ifdef CONFIG_PPC_BOOK3S_64
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/* Exclusive stacks for system reset and machine check exception. */
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void *nmi_emergency_sp;
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void *mc_emergency_sp;
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u16 in_nmi; /* In nmi handler */
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/*
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* Flag to check whether we are in machine check early handler
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* and already using emergency stack.
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*/
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u16 in_mce;
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u8 hmi_event_available; /* HMI event is available */
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u8 hmi_p9_special_emu; /* HMI P9 special emulation */
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#endif
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/* Stuff for accurate time accounting */
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struct cpu_accounting_data accounting;
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u64 dtl_ridx; /* read index in dispatch log */
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struct dtl_entry *dtl_curr; /* pointer corresponding to dtl_ridx */
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#ifdef CONFIG_KVM_BOOK3S_HANDLER
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#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
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/* We use this to store guest state in */
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struct kvmppc_book3s_shadow_vcpu shadow_vcpu;
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#endif
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struct kvmppc_host_state kvm_hstate;
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#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
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/*
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* Bitmap for sibling subcore status. See kvm/book3s_hv_ras.c for
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* more details
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*/
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struct sibling_subcore_state *sibling_subcore_state;
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#endif
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#endif
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#ifdef CONFIG_PPC_BOOK3S_64
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/*
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* rfi fallback flush must be in its own cacheline to prevent
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* other paca data leaking into the L1d
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*/
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u64 exrfi[EX_SIZE] __aligned(0x80);
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void *rfi_flush_fallback_area;
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u64 l1d_flush_size;
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#endif
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};
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extern void copy_mm_to_paca(struct mm_struct *mm);
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extern struct paca_struct *paca;
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extern void initialise_paca(struct paca_struct *new_paca, int cpu);
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extern void setup_paca(struct paca_struct *new_paca);
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extern void allocate_pacas(void);
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extern void free_unused_pacas(void);
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#else /* CONFIG_PPC64 */
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static inline void allocate_pacas(void) { };
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static inline void free_unused_pacas(void) { };
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#endif /* CONFIG_PPC64 */
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_PACA_H */
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