Raanan Avargil 74f31299a4 e1000e: Increase PHY PLL clock gate timing ... Several packet loss issues were reported for which the root cause for them was an incorrect configuration of internal HW PHY clock gating mechanism by SW. This patch provides the correct mechanism. Signed-off-by: Raanan Avargil <raanan.avargil@intel.com> Tested-by: Aaron Brown <aaron.f.brown@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>		2016-02-24 14:44:01 -08:00
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e1000	e1000: Elementary checkpatch warnings and checks removed	2015-12-12 23:13:52 -08:00
e1000e	e1000e: Increase PHY PLL clock gate timing	2016-02-24 14:44:01 -08:00
fm10k	net: rework setup_tc ndo op to consume general tc operand	2016-02-17 09:47:35 -05:00
i40e	i40e/ethtool: support coalesce setting by queue	2016-02-19 22:54:10 -05:00
i40evf	i40e/i40evf: Bump i40e to 1.4.25 and i40evf to 1.4.15	2016-02-19 00:12:07 -08:00
igb	igb: Add workaround for VLAN tag stripping on 82576	2016-02-15 16:52:33 -08:00
igbvf	igb/igbvf: don't give up	2016-02-15 16:17:57 -08:00
ixgb	drivers/net: get rid of unnecessary initializations in .get_drvinfo()	2015-10-16 00:24:10 -07:00
ixgbe	ixgbe: fix dates on header of ixgbe_model.h	2016-02-17 21:44:12 -05:00
ixgbevf	ixgbevf: minor cleanups for ixgbevf_set_itr()	2015-12-29 19:16:05 -08:00
e100.c	e100: Release skb when DMA mapping is failed in e100_xmit_prepare	2015-08-18 14:06:05 -07:00
Kconfig	i40e: Kernel dependency update for i40e to support geneve offload	2015-12-16 10:58:56 -05:00
Makefile	fm10k: Add skeletal frame for Intel(R) FM10000 Ethernet Switch Host Interface Driver	2014-09-23 03:59:13 -07:00