forked from Minki/linux
29746d0125
This patch adds decriptions for mt8183 IOMMU and SMI.
mt8183 has only one M4U like mt8173 and is also MTK IOMMU gen2 which
uses ARM Short-Descriptor translation table format.
The mt8183 M4U-SMI HW diagram is as below:
EMI
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M4U
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----------
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gals0-rx gals1-rx
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gals0-tx gals1-tx
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------------
SMI Common
------------
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+-----+-----+--------+-----+-----+-------+-------+
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| | gals-rx gals-rx | gals-rx gals-rx gals-rx
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| | gals-tx gals-tx | gals-tx gals-tx gals-tx
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larb0 larb1 IPU0 IPU1 larb4 larb5 larb6 CCU
disp vdec img cam venc img cam
All the connections are HW fixed, SW can NOT adjust it.
Compared with mt8173, we add a GALS(Global Async Local Sync) module
between SMI-common and M4U, and additional GALS between larb2/3/5/6
and SMI-common. GALS can help synchronize for the modules in different
clock frequency, it can be seen as a "asynchronous fifo".
GALS can only help transfer the command/data while it doesn't have
the configuring register, thus it has the special "smi" clock and it
doesn't have the "apb" clock. From the diagram above, we add "gals0"
and "gals1" clocks for smi-common and add a "gals" clock for smi-larb.
>From the diagram above, IPU0/IPU1(Image Processor Unit) and CCU(Camera
Control Unit) is connected with smi-common directly, we can take them
as "larb2", "larb3" and "larb7", and their register spaces are
different with the normal larb.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
49 lines
2.0 KiB
Plaintext
49 lines
2.0 KiB
Plaintext
SMI (Smart Multimedia Interface) Common
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The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
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Mediatek SMI have two generations of HW architecture, here is the list
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which generation the SoCs use:
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generation 1: mt2701 and mt7623.
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generation 2: mt2712, mt8173 and mt8183.
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There's slight differences between the two SMI, for generation 2, the
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register which control the iommu port is at each larb's register base. But
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for generation 1, the register is at smi ao base(smi always on register
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base). Besides that, the smi async clock should be prepared and enabled for
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SMI generation 1 to transform the smi clock into emi clock domain, but that is
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not needed for SMI generation 2.
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Required properties:
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- compatible : must be one of :
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"mediatek,mt2701-smi-common"
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"mediatek,mt2712-smi-common"
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"mediatek,mt7623-smi-common", "mediatek,mt2701-smi-common"
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"mediatek,mt8173-smi-common"
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"mediatek,mt8183-smi-common"
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- reg : the register and size of the SMI block.
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- power-domains : a phandle to the power domain of this local arbiter.
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- clocks : Must contain an entry for each entry in clock-names.
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- clock-names : must contain 3 entries for generation 1 smi HW and 2 entries
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for generation 2 smi HW as follows:
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- "apb" : Advanced Peripheral Bus clock, It's the clock for setting
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the register.
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- "smi" : It's the clock for transfer data and command.
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They may be the same if both source clocks are the same.
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- "async" : asynchronous clock, it help transform the smi clock into the emi
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clock domain, this clock is only needed by generation 1 smi HW.
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and these 2 option clocks for generation 2 smi HW:
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- "gals0": the path0 clock of GALS(Global Async Local Sync).
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- "gals1": the path1 clock of GALS(Global Async Local Sync).
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Here is the list which has this GALS: mt8183.
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Example:
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smi_common: smi@14022000 {
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compatible = "mediatek,mt8173-smi-common";
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reg = <0 0x14022000 0 0x1000>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
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clocks = <&mmsys CLK_MM_SMI_COMMON>,
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<&mmsys CLK_MM_SMI_COMMON>;
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clock-names = "apb", "smi";
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};
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