73770ca53f
This change shorten wait time when HPD LOW. With HPD LOW, without this change, AUX routine delay is 450us. With this change, it is 42us. Signed-off-by: Hersen Wu <hersenxs.wu@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
122 lines
3.5 KiB
C
122 lines
3.5 KiB
C
/*
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* Copyright 2012-15 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DAL_ENGINE_H__
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#define __DAL_ENGINE_H__
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enum i2caux_transaction_operation {
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I2CAUX_TRANSACTION_READ,
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I2CAUX_TRANSACTION_WRITE
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};
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enum i2caux_transaction_address_space {
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I2CAUX_TRANSACTION_ADDRESS_SPACE_I2C = 1,
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I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD
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};
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struct i2caux_transaction_payload {
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enum i2caux_transaction_address_space address_space;
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uint32_t address;
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uint32_t length;
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uint8_t *data;
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};
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enum i2caux_transaction_status {
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I2CAUX_TRANSACTION_STATUS_UNKNOWN = (-1L),
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I2CAUX_TRANSACTION_STATUS_SUCCEEDED,
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I2CAUX_TRANSACTION_STATUS_FAILED_CHANNEL_BUSY,
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I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT,
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I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR,
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I2CAUX_TRANSACTION_STATUS_FAILED_NACK,
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I2CAUX_TRANSACTION_STATUS_FAILED_INCOMPLETE,
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I2CAUX_TRANSACTION_STATUS_FAILED_OPERATION,
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I2CAUX_TRANSACTION_STATUS_FAILED_INVALID_OPERATION,
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I2CAUX_TRANSACTION_STATUS_FAILED_BUFFER_OVERFLOW,
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I2CAUX_TRANSACTION_STATUS_FAILED_HPD_DISCON
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};
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struct i2caux_transaction_request {
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enum i2caux_transaction_operation operation;
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struct i2caux_transaction_payload payload;
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enum i2caux_transaction_status status;
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};
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enum i2caux_engine_type {
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I2CAUX_ENGINE_TYPE_UNKNOWN = (-1L),
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I2CAUX_ENGINE_TYPE_AUX,
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I2CAUX_ENGINE_TYPE_I2C_DDC_HW,
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I2CAUX_ENGINE_TYPE_I2C_GENERIC_HW,
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I2CAUX_ENGINE_TYPE_I2C_SW
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};
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enum i2c_default_speed {
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I2CAUX_DEFAULT_I2C_HW_SPEED = 50,
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I2CAUX_DEFAULT_I2C_SW_SPEED = 50
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};
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enum i2caux_transaction_action {
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I2CAUX_TRANSACTION_ACTION_I2C_WRITE = 0x00,
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I2CAUX_TRANSACTION_ACTION_I2C_READ = 0x10,
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I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST = 0x20,
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I2CAUX_TRANSACTION_ACTION_I2C_WRITE_MOT = 0x40,
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I2CAUX_TRANSACTION_ACTION_I2C_READ_MOT = 0x50,
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I2CAUX_TRANSACTION_ACTION_I2C_STATUS_REQUEST_MOT = 0x60,
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I2CAUX_TRANSACTION_ACTION_DP_WRITE = 0x80,
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I2CAUX_TRANSACTION_ACTION_DP_READ = 0x90
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};
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struct engine;
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struct engine_funcs {
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enum i2caux_engine_type (*get_engine_type)(
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const struct engine *engine);
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bool (*acquire)(
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struct engine *engine,
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struct ddc *ddc);
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bool (*submit_request)(
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struct engine *engine,
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struct i2caux_transaction_request *request,
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bool middle_of_transaction);
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void (*release_engine)(
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struct engine *engine);
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};
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struct engine {
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const struct engine_funcs *funcs;
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struct ddc *ddc;
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struct dc_context *ctx;
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};
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void dal_i2caux_construct_engine(
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struct engine *engine,
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struct dc_context *ctx);
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void dal_i2caux_destruct_engine(
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struct engine *engine);
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#endif
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