731a927438
The LP1 suspend mode will power off the CPU, clock gated the PLLs and put SDRAM to self-refresh mode. Any interrupt can wake up device from LP1. The sequence when LP1 suspending: * tunning off L1 data cache and the MMU * putting SDRAM into self-refresh * storing some EMC registers and SCLK burst policy * switching CPU to CLK_M (12MHz OSC) * switching SCLK to CLK_S (32KHz OSC) * tunning off PLLM, PLLP and PLLC * shutting off the CPU rail The sequence of LP1 resuming: * re-enabling PLLM, PLLP, and PLLC * restoring some EMC registers and SCLK burst policy * setting up CCLK burst policy to PLLP * resuming SDRAM to normal mode * jumping to the "tegra_resume" from PMC_SCRATCH41 Due to the SDRAM will be put into self-refresh mode, the low level procedures of LP1 suspending and resuming should be copied to TEGRA_IRAM_CODE_AREA (TEGRA_IRAM_BASE + SZ_4K) when suspending. Before restoring the CPU context when resuming, the SDRAM needs to be switched back to normal mode. And the PLLs need to be re-enabled, SCLK burst policy be restored, CCLK burst policy be set in PLLP. Then jumping to "tegra_resume" that was expected to be stored in PMC_SCRATCH41 to restore CPU context and back to kernel. Based on the work by: Colin Cross <ccross@android.com> Gary King <gking@nvidia.com> Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
43 lines
1.4 KiB
Makefile
43 lines
1.4 KiB
Makefile
asflags-y += -march=armv7-a
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obj-y += common.o
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obj-y += io.o
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obj-y += irq.o
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obj-y += fuse.o
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obj-y += pmc.o
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obj-y += flowctrl.o
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obj-y += powergate.o
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obj-y += apbio.o
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obj-y += pm.o
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obj-y += reset.o
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obj-y += reset-handler.o
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obj-y += sleep.o
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obj-y += tegra.o
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obj-$(CONFIG_CPU_IDLE) += cpuidle.o
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obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_speedo.o
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obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o
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obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += sleep-tegra20.o
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obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pm-tegra20.o
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ifeq ($(CONFIG_CPU_IDLE),y)
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obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += cpuidle-tegra20.o
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endif
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obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_speedo.o
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obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += sleep-tegra30.o
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obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pm-tegra30.o
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ifeq ($(CONFIG_CPU_IDLE),y)
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obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += cpuidle-tegra30.o
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endif
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obj-$(CONFIG_SMP) += platsmp.o headsmp.o
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obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
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obj-$(CONFIG_TEGRA_PCI) += pcie.o
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obj-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114_speedo.o
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obj-$(CONFIG_ARCH_TEGRA_114_SOC) += sleep-tegra30.o
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ifeq ($(CONFIG_CPU_IDLE),y)
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obj-$(CONFIG_ARCH_TEGRA_114_SOC) += cpuidle-tegra114.o
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endif
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obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-harmony-pcie.o
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obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-paz00.o
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