forked from Minki/linux
252f4bf400
Conflicts: drivers/net/wireless/ath/ar9170/main.c drivers/net/wireless/ath/ar9170/phy.c drivers/net/wireless/zd1211rw/zd_rf_rf2959.c
307 lines
9.4 KiB
C
307 lines
9.4 KiB
C
/******************************************************************************
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
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* USA
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*
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* The full GNU General Public License is included in this distribution
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* in the file called LICENSE.GPL.
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*
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* Contact Information:
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* Intel Linux Wireless <ilw@linux.intel.com>
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* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*****************************************************************************/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/etherdevice.h>
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#include <linux/sched.h>
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#include <linux/gfp.h>
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#include <net/mac80211.h>
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#include "iwl-dev.h"
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#include "iwl-core.h"
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#include "iwl-agn.h"
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#include "iwl-helpers.h"
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#define ICT_COUNT (PAGE_SIZE/sizeof(u32))
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/* Free dram table */
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void iwl_free_isr_ict(struct iwl_priv *priv)
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{
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if (priv->_agn.ict_tbl_vir) {
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dma_free_coherent(&priv->pci_dev->dev,
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(sizeof(u32) * ICT_COUNT) + PAGE_SIZE,
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priv->_agn.ict_tbl_vir,
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priv->_agn.ict_tbl_dma);
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priv->_agn.ict_tbl_vir = NULL;
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}
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}
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/* allocate dram shared table it is a PAGE_SIZE aligned
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* also reset all data related to ICT table interrupt.
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*/
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int iwl_alloc_isr_ict(struct iwl_priv *priv)
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{
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/* allocate shrared data table */
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priv->_agn.ict_tbl_vir =
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dma_alloc_coherent(&priv->pci_dev->dev,
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(sizeof(u32) * ICT_COUNT) + PAGE_SIZE,
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&priv->_agn.ict_tbl_dma, GFP_KERNEL);
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if (!priv->_agn.ict_tbl_vir)
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return -ENOMEM;
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/* align table to PAGE_SIZE boundary */
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priv->_agn.aligned_ict_tbl_dma = ALIGN(priv->_agn.ict_tbl_dma, PAGE_SIZE);
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IWL_DEBUG_ISR(priv, "ict dma addr %Lx dma aligned %Lx diff %d\n",
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(unsigned long long)priv->_agn.ict_tbl_dma,
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(unsigned long long)priv->_agn.aligned_ict_tbl_dma,
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(int)(priv->_agn.aligned_ict_tbl_dma - priv->_agn.ict_tbl_dma));
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priv->_agn.ict_tbl = priv->_agn.ict_tbl_vir +
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(priv->_agn.aligned_ict_tbl_dma - priv->_agn.ict_tbl_dma);
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IWL_DEBUG_ISR(priv, "ict vir addr %p vir aligned %p diff %d\n",
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priv->_agn.ict_tbl, priv->_agn.ict_tbl_vir,
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(int)(priv->_agn.aligned_ict_tbl_dma - priv->_agn.ict_tbl_dma));
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/* reset table and index to all 0 */
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memset(priv->_agn.ict_tbl_vir,0, (sizeof(u32) * ICT_COUNT) + PAGE_SIZE);
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priv->_agn.ict_index = 0;
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/* add periodic RX interrupt */
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priv->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
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return 0;
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}
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/* Device is going up inform it about using ICT interrupt table,
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* also we need to tell the driver to start using ICT interrupt.
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*/
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int iwl_reset_ict(struct iwl_priv *priv)
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{
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u32 val;
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unsigned long flags;
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if (!priv->_agn.ict_tbl_vir)
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return 0;
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spin_lock_irqsave(&priv->lock, flags);
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iwl_disable_interrupts(priv);
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memset(&priv->_agn.ict_tbl[0], 0, sizeof(u32) * ICT_COUNT);
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val = priv->_agn.aligned_ict_tbl_dma >> PAGE_SHIFT;
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val |= CSR_DRAM_INT_TBL_ENABLE;
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val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
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IWL_DEBUG_ISR(priv, "CSR_DRAM_INT_TBL_REG =0x%X "
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"aligned dma address %Lx\n",
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val, (unsigned long long)priv->_agn.aligned_ict_tbl_dma);
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iwl_write32(priv, CSR_DRAM_INT_TBL_REG, val);
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priv->_agn.use_ict = true;
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priv->_agn.ict_index = 0;
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iwl_write32(priv, CSR_INT, priv->inta_mask);
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iwl_enable_interrupts(priv);
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spin_unlock_irqrestore(&priv->lock, flags);
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return 0;
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}
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/* Device is going down disable ict interrupt usage */
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void iwl_disable_ict(struct iwl_priv *priv)
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{
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unsigned long flags;
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spin_lock_irqsave(&priv->lock, flags);
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priv->_agn.use_ict = false;
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spin_unlock_irqrestore(&priv->lock, flags);
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}
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static irqreturn_t iwl_isr(int irq, void *data)
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{
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struct iwl_priv *priv = data;
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u32 inta, inta_mask;
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unsigned long flags;
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#ifdef CONFIG_IWLWIFI_DEBUG
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u32 inta_fh;
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#endif
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if (!priv)
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return IRQ_NONE;
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spin_lock_irqsave(&priv->lock, flags);
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/* Disable (but don't clear!) interrupts here to avoid
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* back-to-back ISRs and sporadic interrupts from our NIC.
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* If we have something to service, the tasklet will re-enable ints.
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* If we *don't* have something, we'll re-enable before leaving here. */
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inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
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iwl_write32(priv, CSR_INT_MASK, 0x00000000);
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/* Discover which interrupts are active/pending */
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inta = iwl_read32(priv, CSR_INT);
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/* Ignore interrupt if there's nothing in NIC to service.
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* This may be due to IRQ shared with another device,
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* or due to sporadic interrupts thrown from our NIC. */
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if (!inta) {
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IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
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goto none;
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}
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if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
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/* Hardware disappeared. It might have already raised
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* an interrupt */
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IWL_WARN(priv, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
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goto unplugged;
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}
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#ifdef CONFIG_IWLWIFI_DEBUG
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if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
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inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
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IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x, "
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"fh 0x%08x\n", inta, inta_mask, inta_fh);
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}
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#endif
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priv->_agn.inta |= inta;
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/* iwl_irq_tasklet() will service interrupts and re-enable them */
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if (likely(inta))
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tasklet_schedule(&priv->irq_tasklet);
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else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->_agn.inta)
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iwl_enable_interrupts(priv);
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unplugged:
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spin_unlock_irqrestore(&priv->lock, flags);
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return IRQ_HANDLED;
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none:
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/* re-enable interrupts here since we don't have anything to service. */
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/* only Re-enable if disabled by irq and no schedules tasklet. */
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if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->_agn.inta)
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iwl_enable_interrupts(priv);
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spin_unlock_irqrestore(&priv->lock, flags);
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return IRQ_NONE;
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}
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/* interrupt handler using ict table, with this interrupt driver will
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* stop using INTA register to get device's interrupt, reading this register
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* is expensive, device will write interrupts in ICT dram table, increment
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* index then will fire interrupt to driver, driver will OR all ICT table
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* entries from current index up to table entry with 0 value. the result is
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* the interrupt we need to service, driver will set the entries back to 0 and
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* set index.
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*/
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irqreturn_t iwl_isr_ict(int irq, void *data)
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{
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struct iwl_priv *priv = data;
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u32 inta, inta_mask;
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u32 val = 0;
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unsigned long flags;
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if (!priv)
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return IRQ_NONE;
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/* dram interrupt table not set yet,
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* use legacy interrupt.
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*/
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if (!priv->_agn.use_ict)
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return iwl_isr(irq, data);
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spin_lock_irqsave(&priv->lock, flags);
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/* Disable (but don't clear!) interrupts here to avoid
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* back-to-back ISRs and sporadic interrupts from our NIC.
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* If we have something to service, the tasklet will re-enable ints.
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* If we *don't* have something, we'll re-enable before leaving here.
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*/
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inta_mask = iwl_read32(priv, CSR_INT_MASK); /* just for debug */
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iwl_write32(priv, CSR_INT_MASK, 0x00000000);
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/* Ignore interrupt if there's nothing in NIC to service.
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* This may be due to IRQ shared with another device,
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* or due to sporadic interrupts thrown from our NIC. */
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if (!priv->_agn.ict_tbl[priv->_agn.ict_index]) {
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IWL_DEBUG_ISR(priv, "Ignore interrupt, inta == 0\n");
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goto none;
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}
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/* read all entries that not 0 start with ict_index */
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while (priv->_agn.ict_tbl[priv->_agn.ict_index]) {
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val |= le32_to_cpu(priv->_agn.ict_tbl[priv->_agn.ict_index]);
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IWL_DEBUG_ISR(priv, "ICT index %d value 0x%08X\n",
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priv->_agn.ict_index,
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le32_to_cpu(priv->_agn.ict_tbl[priv->_agn.ict_index]));
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priv->_agn.ict_tbl[priv->_agn.ict_index] = 0;
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priv->_agn.ict_index = iwl_queue_inc_wrap(priv->_agn.ict_index,
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ICT_COUNT);
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}
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/* We should not get this value, just ignore it. */
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if (val == 0xffffffff)
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val = 0;
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/*
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* this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
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* (bit 15 before shifting it to 31) to clear when using interrupt
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* coalescing. fortunately, bits 18 and 19 stay set when this happens
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* so we use them to decide on the real state of the Rx bit.
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* In order words, bit 15 is set if bit 18 or bit 19 are set.
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*/
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if (val & 0xC0000)
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val |= 0x8000;
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inta = (0xff & val) | ((0xff00 & val) << 16);
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IWL_DEBUG_ISR(priv, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
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inta, inta_mask, val);
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inta &= priv->inta_mask;
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priv->_agn.inta |= inta;
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/* iwl_irq_tasklet() will service interrupts and re-enable them */
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if (likely(inta))
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tasklet_schedule(&priv->irq_tasklet);
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else if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->_agn.inta) {
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/* Allow interrupt if was disabled by this handler and
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* no tasklet was schedules, We should not enable interrupt,
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* tasklet will enable it.
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*/
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iwl_enable_interrupts(priv);
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}
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spin_unlock_irqrestore(&priv->lock, flags);
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return IRQ_HANDLED;
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none:
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/* re-enable interrupts here since we don't have anything to service.
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* only Re-enable if disabled by irq.
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*/
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if (test_bit(STATUS_INT_ENABLED, &priv->status) && !priv->_agn.inta)
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iwl_enable_interrupts(priv);
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spin_unlock_irqrestore(&priv->lock, flags);
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return IRQ_NONE;
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}
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