forked from Minki/linux
1273 lines
35 KiB
C
1273 lines
35 KiB
C
/* $Id: sbus.c,v 1.19 2002/01/23 11:27:32 davem Exp $
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* sbus.c: UltraSparc SBUS controller support.
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*
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* Copyright (C) 1999 David S. Miller (davem@redhat.com)
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/mm.h>
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#include <linux/spinlock.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <asm/page.h>
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#include <asm/sbus.h>
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#include <asm/io.h>
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#include <asm/upa.h>
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#include <asm/cache.h>
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#include <asm/dma.h>
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#include <asm/irq.h>
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#include <asm/prom.h>
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#include <asm/starfire.h>
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#include "iommu_common.h"
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/* These should be allocated on an SMP_CACHE_BYTES
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* aligned boundary for optimal performance.
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*
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* On SYSIO, using an 8K page size we have 1GB of SBUS
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* DMA space mapped. We divide this space into equally
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* sized clusters. We allocate a DMA mapping from the
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* cluster that matches the order of the allocation, or
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* if the order is greater than the number of clusters,
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* we try to allocate from the last cluster.
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*/
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#define NCLUSTERS 8UL
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#define ONE_GIG (1UL * 1024UL * 1024UL * 1024UL)
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#define CLUSTER_SIZE (ONE_GIG / NCLUSTERS)
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#define CLUSTER_MASK (CLUSTER_SIZE - 1)
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#define CLUSTER_NPAGES (CLUSTER_SIZE >> IO_PAGE_SHIFT)
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#define MAP_BASE ((u32)0xc0000000)
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struct sbus_iommu {
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/*0x00*/spinlock_t lock;
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/*0x08*/iopte_t *page_table;
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/*0x10*/unsigned long strbuf_regs;
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/*0x18*/unsigned long iommu_regs;
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/*0x20*/unsigned long sbus_control_reg;
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/*0x28*/volatile unsigned long strbuf_flushflag;
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/* If NCLUSTERS is ever decresed to 4 or lower,
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* you must increase the size of the type of
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* these counters. You have been duly warned. -DaveM
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*/
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/*0x30*/struct {
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u16 next;
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u16 flush;
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} alloc_info[NCLUSTERS];
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/* The lowest used consistent mapping entry. Since
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* we allocate consistent maps out of cluster 0 this
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* is relative to the beginning of closter 0.
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*/
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/*0x50*/u32 lowest_consistent_map;
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};
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/* Offsets from iommu_regs */
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#define SYSIO_IOMMUREG_BASE 0x2400UL
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#define IOMMU_CONTROL (0x2400UL - 0x2400UL) /* IOMMU control register */
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#define IOMMU_TSBBASE (0x2408UL - 0x2400UL) /* TSB base address register */
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#define IOMMU_FLUSH (0x2410UL - 0x2400UL) /* IOMMU flush register */
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#define IOMMU_VADIAG (0x4400UL - 0x2400UL) /* SBUS virtual address diagnostic */
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#define IOMMU_TAGCMP (0x4408UL - 0x2400UL) /* TLB tag compare diagnostics */
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#define IOMMU_LRUDIAG (0x4500UL - 0x2400UL) /* IOMMU LRU queue diagnostics */
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#define IOMMU_TAGDIAG (0x4580UL - 0x2400UL) /* TLB tag diagnostics */
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#define IOMMU_DRAMDIAG (0x4600UL - 0x2400UL) /* TLB data RAM diagnostics */
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#define IOMMU_DRAM_VALID (1UL << 30UL)
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static void __iommu_flushall(struct sbus_iommu *iommu)
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{
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unsigned long tag = iommu->iommu_regs + IOMMU_TAGDIAG;
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int entry;
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for (entry = 0; entry < 16; entry++) {
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upa_writeq(0, tag);
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tag += 8UL;
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}
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upa_readq(iommu->sbus_control_reg);
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for (entry = 0; entry < NCLUSTERS; entry++) {
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iommu->alloc_info[entry].flush =
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iommu->alloc_info[entry].next;
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}
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}
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static void iommu_flush(struct sbus_iommu *iommu, u32 base, unsigned long npages)
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{
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while (npages--)
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upa_writeq(base + (npages << IO_PAGE_SHIFT),
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iommu->iommu_regs + IOMMU_FLUSH);
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upa_readq(iommu->sbus_control_reg);
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}
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/* Offsets from strbuf_regs */
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#define SYSIO_STRBUFREG_BASE 0x2800UL
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#define STRBUF_CONTROL (0x2800UL - 0x2800UL) /* Control */
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#define STRBUF_PFLUSH (0x2808UL - 0x2800UL) /* Page flush/invalidate */
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#define STRBUF_FSYNC (0x2810UL - 0x2800UL) /* Flush synchronization */
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#define STRBUF_DRAMDIAG (0x5000UL - 0x2800UL) /* data RAM diagnostic */
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#define STRBUF_ERRDIAG (0x5400UL - 0x2800UL) /* error status diagnostics */
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#define STRBUF_PTAGDIAG (0x5800UL - 0x2800UL) /* Page tag diagnostics */
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#define STRBUF_LTAGDIAG (0x5900UL - 0x2800UL) /* Line tag diagnostics */
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#define STRBUF_TAG_VALID 0x02UL
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static void sbus_strbuf_flush(struct sbus_iommu *iommu, u32 base, unsigned long npages, int direction)
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{
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unsigned long n;
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int limit;
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n = npages;
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while (n--)
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upa_writeq(base + (n << IO_PAGE_SHIFT),
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iommu->strbuf_regs + STRBUF_PFLUSH);
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/* If the device could not have possibly put dirty data into
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* the streaming cache, no flush-flag synchronization needs
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* to be performed.
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*/
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if (direction == SBUS_DMA_TODEVICE)
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return;
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iommu->strbuf_flushflag = 0UL;
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/* Whoopee cushion! */
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upa_writeq(__pa(&iommu->strbuf_flushflag),
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iommu->strbuf_regs + STRBUF_FSYNC);
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upa_readq(iommu->sbus_control_reg);
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limit = 100000;
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while (iommu->strbuf_flushflag == 0UL) {
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limit--;
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if (!limit)
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break;
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udelay(1);
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rmb();
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}
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if (!limit)
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printk(KERN_WARNING "sbus_strbuf_flush: flushflag timeout "
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"vaddr[%08x] npages[%ld]\n",
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base, npages);
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}
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static iopte_t *alloc_streaming_cluster(struct sbus_iommu *iommu, unsigned long npages)
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{
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iopte_t *iopte, *limit, *first, *cluster;
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unsigned long cnum, ent, nent, flush_point, found;
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cnum = 0;
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nent = 1;
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while ((1UL << cnum) < npages)
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cnum++;
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if(cnum >= NCLUSTERS) {
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nent = 1UL << (cnum - NCLUSTERS);
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cnum = NCLUSTERS - 1;
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}
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iopte = iommu->page_table + (cnum * CLUSTER_NPAGES);
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if (cnum == 0)
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limit = (iommu->page_table +
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iommu->lowest_consistent_map);
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else
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limit = (iopte + CLUSTER_NPAGES);
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iopte += ((ent = iommu->alloc_info[cnum].next) << cnum);
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flush_point = iommu->alloc_info[cnum].flush;
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first = iopte;
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cluster = NULL;
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found = 0;
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for (;;) {
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if (iopte_val(*iopte) == 0UL) {
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found++;
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if (!cluster)
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cluster = iopte;
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} else {
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/* Used cluster in the way */
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cluster = NULL;
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found = 0;
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}
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if (found == nent)
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break;
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iopte += (1 << cnum);
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ent++;
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if (iopte >= limit) {
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iopte = (iommu->page_table + (cnum * CLUSTER_NPAGES));
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ent = 0;
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/* Multiple cluster allocations must not wrap */
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cluster = NULL;
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found = 0;
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}
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if (ent == flush_point)
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__iommu_flushall(iommu);
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if (iopte == first)
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goto bad;
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}
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/* ent/iopte points to the last cluster entry we're going to use,
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* so save our place for the next allocation.
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*/
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if ((iopte + (1 << cnum)) >= limit)
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ent = 0;
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else
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ent = ent + 1;
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iommu->alloc_info[cnum].next = ent;
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if (ent == flush_point)
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__iommu_flushall(iommu);
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/* I've got your streaming cluster right here buddy boy... */
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return cluster;
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bad:
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printk(KERN_EMERG "sbus: alloc_streaming_cluster of npages(%ld) failed!\n",
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npages);
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return NULL;
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}
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static void free_streaming_cluster(struct sbus_iommu *iommu, u32 base, unsigned long npages)
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{
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unsigned long cnum, ent, nent;
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iopte_t *iopte;
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cnum = 0;
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nent = 1;
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while ((1UL << cnum) < npages)
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cnum++;
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if(cnum >= NCLUSTERS) {
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nent = 1UL << (cnum - NCLUSTERS);
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cnum = NCLUSTERS - 1;
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}
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ent = (base & CLUSTER_MASK) >> (IO_PAGE_SHIFT + cnum);
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iopte = iommu->page_table + ((base - MAP_BASE) >> IO_PAGE_SHIFT);
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do {
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iopte_val(*iopte) = 0UL;
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iopte += 1 << cnum;
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} while(--nent);
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/* If the global flush might not have caught this entry,
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* adjust the flush point such that we will flush before
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* ever trying to reuse it.
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*/
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#define between(X,Y,Z) (((Z) - (Y)) >= ((X) - (Y)))
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if (between(ent, iommu->alloc_info[cnum].next, iommu->alloc_info[cnum].flush))
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iommu->alloc_info[cnum].flush = ent;
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#undef between
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}
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/* We allocate consistent mappings from the end of cluster zero. */
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static iopte_t *alloc_consistent_cluster(struct sbus_iommu *iommu, unsigned long npages)
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{
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iopte_t *iopte;
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iopte = iommu->page_table + (1 * CLUSTER_NPAGES);
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while (iopte > iommu->page_table) {
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iopte--;
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if (!(iopte_val(*iopte) & IOPTE_VALID)) {
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unsigned long tmp = npages;
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while (--tmp) {
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iopte--;
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if (iopte_val(*iopte) & IOPTE_VALID)
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break;
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}
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if (tmp == 0) {
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u32 entry = (iopte - iommu->page_table);
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if (entry < iommu->lowest_consistent_map)
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iommu->lowest_consistent_map = entry;
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return iopte;
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}
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}
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}
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return NULL;
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}
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static void free_consistent_cluster(struct sbus_iommu *iommu, u32 base, unsigned long npages)
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{
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iopte_t *iopte = iommu->page_table + ((base - MAP_BASE) >> IO_PAGE_SHIFT);
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if ((iopte - iommu->page_table) == iommu->lowest_consistent_map) {
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iopte_t *walk = iopte + npages;
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iopte_t *limit;
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limit = iommu->page_table + CLUSTER_NPAGES;
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while (walk < limit) {
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if (iopte_val(*walk) != 0UL)
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break;
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walk++;
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}
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iommu->lowest_consistent_map =
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(walk - iommu->page_table);
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}
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while (npages--)
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*iopte++ = __iopte(0UL);
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}
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void *sbus_alloc_consistent(struct sbus_dev *sdev, size_t size, dma_addr_t *dvma_addr)
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{
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unsigned long order, first_page, flags;
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struct sbus_iommu *iommu;
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iopte_t *iopte;
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void *ret;
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int npages;
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if (size <= 0 || sdev == NULL || dvma_addr == NULL)
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return NULL;
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size = IO_PAGE_ALIGN(size);
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order = get_order(size);
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if (order >= 10)
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return NULL;
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first_page = __get_free_pages(GFP_KERNEL|__GFP_COMP, order);
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if (first_page == 0UL)
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return NULL;
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memset((char *)first_page, 0, PAGE_SIZE << order);
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iommu = sdev->bus->iommu;
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spin_lock_irqsave(&iommu->lock, flags);
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iopte = alloc_consistent_cluster(iommu, size >> IO_PAGE_SHIFT);
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if (iopte == NULL) {
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spin_unlock_irqrestore(&iommu->lock, flags);
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free_pages(first_page, order);
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return NULL;
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}
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/* Ok, we're committed at this point. */
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*dvma_addr = MAP_BASE + ((iopte - iommu->page_table) << IO_PAGE_SHIFT);
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ret = (void *) first_page;
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npages = size >> IO_PAGE_SHIFT;
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while (npages--) {
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*iopte++ = __iopte(IOPTE_VALID | IOPTE_CACHE | IOPTE_WRITE |
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(__pa(first_page) & IOPTE_PAGE));
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first_page += IO_PAGE_SIZE;
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}
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iommu_flush(iommu, *dvma_addr, size >> IO_PAGE_SHIFT);
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spin_unlock_irqrestore(&iommu->lock, flags);
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return ret;
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}
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void sbus_free_consistent(struct sbus_dev *sdev, size_t size, void *cpu, dma_addr_t dvma)
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{
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unsigned long order, npages;
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struct sbus_iommu *iommu;
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if (size <= 0 || sdev == NULL || cpu == NULL)
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return;
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npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
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iommu = sdev->bus->iommu;
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spin_lock_irq(&iommu->lock);
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free_consistent_cluster(iommu, dvma, npages);
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iommu_flush(iommu, dvma, npages);
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spin_unlock_irq(&iommu->lock);
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order = get_order(size);
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if (order < 10)
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free_pages((unsigned long)cpu, order);
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}
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dma_addr_t sbus_map_single(struct sbus_dev *sdev, void *ptr, size_t size, int dir)
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{
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struct sbus_iommu *iommu = sdev->bus->iommu;
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unsigned long npages, pbase, flags;
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iopte_t *iopte;
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u32 dma_base, offset;
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unsigned long iopte_bits;
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if (dir == SBUS_DMA_NONE)
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BUG();
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pbase = (unsigned long) ptr;
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offset = (u32) (pbase & ~IO_PAGE_MASK);
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size = (IO_PAGE_ALIGN(pbase + size) - (pbase & IO_PAGE_MASK));
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pbase = (unsigned long) __pa(pbase & IO_PAGE_MASK);
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spin_lock_irqsave(&iommu->lock, flags);
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npages = size >> IO_PAGE_SHIFT;
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iopte = alloc_streaming_cluster(iommu, npages);
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if (iopte == NULL)
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goto bad;
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dma_base = MAP_BASE + ((iopte - iommu->page_table) << IO_PAGE_SHIFT);
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npages = size >> IO_PAGE_SHIFT;
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iopte_bits = IOPTE_VALID | IOPTE_STBUF | IOPTE_CACHE;
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if (dir != SBUS_DMA_TODEVICE)
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iopte_bits |= IOPTE_WRITE;
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while (npages--) {
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*iopte++ = __iopte(iopte_bits | (pbase & IOPTE_PAGE));
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pbase += IO_PAGE_SIZE;
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}
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npages = size >> IO_PAGE_SHIFT;
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spin_unlock_irqrestore(&iommu->lock, flags);
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return (dma_base | offset);
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bad:
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spin_unlock_irqrestore(&iommu->lock, flags);
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BUG();
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return 0;
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}
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void sbus_unmap_single(struct sbus_dev *sdev, dma_addr_t dma_addr, size_t size, int direction)
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{
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struct sbus_iommu *iommu = sdev->bus->iommu;
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u32 dma_base = dma_addr & IO_PAGE_MASK;
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unsigned long flags;
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size = (IO_PAGE_ALIGN(dma_addr + size) - dma_base);
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spin_lock_irqsave(&iommu->lock, flags);
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free_streaming_cluster(iommu, dma_base, size >> IO_PAGE_SHIFT);
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sbus_strbuf_flush(iommu, dma_base, size >> IO_PAGE_SHIFT, direction);
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spin_unlock_irqrestore(&iommu->lock, flags);
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}
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#define SG_ENT_PHYS_ADDRESS(SG) \
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(__pa(page_address((SG)->page)) + (SG)->offset)
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static inline void fill_sg(iopte_t *iopte, struct scatterlist *sg, int nused, int nelems, unsigned long iopte_bits)
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{
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struct scatterlist *dma_sg = sg;
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struct scatterlist *sg_end = sg + nelems;
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int i;
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for (i = 0; i < nused; i++) {
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unsigned long pteval = ~0UL;
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u32 dma_npages;
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dma_npages = ((dma_sg->dma_address & (IO_PAGE_SIZE - 1UL)) +
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dma_sg->dma_length +
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((IO_PAGE_SIZE - 1UL))) >> IO_PAGE_SHIFT;
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do {
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unsigned long offset;
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signed int len;
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/* If we are here, we know we have at least one
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* more page to map. So walk forward until we
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* hit a page crossing, and begin creating new
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* mappings from that spot.
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*/
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for (;;) {
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unsigned long tmp;
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tmp = (unsigned long) SG_ENT_PHYS_ADDRESS(sg);
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len = sg->length;
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if (((tmp ^ pteval) >> IO_PAGE_SHIFT) != 0UL) {
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pteval = tmp & IO_PAGE_MASK;
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offset = tmp & (IO_PAGE_SIZE - 1UL);
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break;
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}
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if (((tmp ^ (tmp + len - 1UL)) >> IO_PAGE_SHIFT) != 0UL) {
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pteval = (tmp + IO_PAGE_SIZE) & IO_PAGE_MASK;
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offset = 0UL;
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len -= (IO_PAGE_SIZE - (tmp & (IO_PAGE_SIZE - 1UL)));
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break;
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}
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sg++;
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}
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pteval = ((pteval & IOPTE_PAGE) | iopte_bits);
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while (len > 0) {
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*iopte++ = __iopte(pteval);
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pteval += IO_PAGE_SIZE;
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len -= (IO_PAGE_SIZE - offset);
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offset = 0;
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dma_npages--;
|
|
}
|
|
|
|
pteval = (pteval & IOPTE_PAGE) + len;
|
|
sg++;
|
|
|
|
/* Skip over any tail mappings we've fully mapped,
|
|
* adjusting pteval along the way. Stop when we
|
|
* detect a page crossing event.
|
|
*/
|
|
while (sg < sg_end &&
|
|
(pteval << (64 - IO_PAGE_SHIFT)) != 0UL &&
|
|
(pteval == SG_ENT_PHYS_ADDRESS(sg)) &&
|
|
((pteval ^
|
|
(SG_ENT_PHYS_ADDRESS(sg) + sg->length - 1UL)) >> IO_PAGE_SHIFT) == 0UL) {
|
|
pteval += sg->length;
|
|
sg++;
|
|
}
|
|
if ((pteval << (64 - IO_PAGE_SHIFT)) == 0UL)
|
|
pteval = ~0UL;
|
|
} while (dma_npages != 0);
|
|
dma_sg++;
|
|
}
|
|
}
|
|
|
|
int sbus_map_sg(struct sbus_dev *sdev, struct scatterlist *sg, int nents, int dir)
|
|
{
|
|
struct sbus_iommu *iommu = sdev->bus->iommu;
|
|
unsigned long flags, npages;
|
|
iopte_t *iopte;
|
|
u32 dma_base;
|
|
struct scatterlist *sgtmp;
|
|
int used;
|
|
unsigned long iopte_bits;
|
|
|
|
if (dir == SBUS_DMA_NONE)
|
|
BUG();
|
|
|
|
/* Fast path single entry scatterlists. */
|
|
if (nents == 1) {
|
|
sg->dma_address =
|
|
sbus_map_single(sdev,
|
|
(page_address(sg->page) + sg->offset),
|
|
sg->length, dir);
|
|
sg->dma_length = sg->length;
|
|
return 1;
|
|
}
|
|
|
|
npages = prepare_sg(sg, nents);
|
|
|
|
spin_lock_irqsave(&iommu->lock, flags);
|
|
iopte = alloc_streaming_cluster(iommu, npages);
|
|
if (iopte == NULL)
|
|
goto bad;
|
|
dma_base = MAP_BASE + ((iopte - iommu->page_table) << IO_PAGE_SHIFT);
|
|
|
|
/* Normalize DVMA addresses. */
|
|
sgtmp = sg;
|
|
used = nents;
|
|
|
|
while (used && sgtmp->dma_length) {
|
|
sgtmp->dma_address += dma_base;
|
|
sgtmp++;
|
|
used--;
|
|
}
|
|
used = nents - used;
|
|
|
|
iopte_bits = IOPTE_VALID | IOPTE_STBUF | IOPTE_CACHE;
|
|
if (dir != SBUS_DMA_TODEVICE)
|
|
iopte_bits |= IOPTE_WRITE;
|
|
|
|
fill_sg(iopte, sg, used, nents, iopte_bits);
|
|
#ifdef VERIFY_SG
|
|
verify_sglist(sg, nents, iopte, npages);
|
|
#endif
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
|
|
return used;
|
|
|
|
bad:
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
BUG();
|
|
return 0;
|
|
}
|
|
|
|
void sbus_unmap_sg(struct sbus_dev *sdev, struct scatterlist *sg, int nents, int direction)
|
|
{
|
|
unsigned long size, flags;
|
|
struct sbus_iommu *iommu;
|
|
u32 dvma_base;
|
|
int i;
|
|
|
|
/* Fast path single entry scatterlists. */
|
|
if (nents == 1) {
|
|
sbus_unmap_single(sdev, sg->dma_address, sg->dma_length, direction);
|
|
return;
|
|
}
|
|
|
|
dvma_base = sg[0].dma_address & IO_PAGE_MASK;
|
|
for (i = 0; i < nents; i++) {
|
|
if (sg[i].dma_length == 0)
|
|
break;
|
|
}
|
|
i--;
|
|
size = IO_PAGE_ALIGN(sg[i].dma_address + sg[i].dma_length) - dvma_base;
|
|
|
|
iommu = sdev->bus->iommu;
|
|
spin_lock_irqsave(&iommu->lock, flags);
|
|
free_streaming_cluster(iommu, dvma_base, size >> IO_PAGE_SHIFT);
|
|
sbus_strbuf_flush(iommu, dvma_base, size >> IO_PAGE_SHIFT, direction);
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
}
|
|
|
|
void sbus_dma_sync_single_for_cpu(struct sbus_dev *sdev, dma_addr_t base, size_t size, int direction)
|
|
{
|
|
struct sbus_iommu *iommu = sdev->bus->iommu;
|
|
unsigned long flags;
|
|
|
|
size = (IO_PAGE_ALIGN(base + size) - (base & IO_PAGE_MASK));
|
|
|
|
spin_lock_irqsave(&iommu->lock, flags);
|
|
sbus_strbuf_flush(iommu, base & IO_PAGE_MASK, size >> IO_PAGE_SHIFT, direction);
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
}
|
|
|
|
void sbus_dma_sync_single_for_device(struct sbus_dev *sdev, dma_addr_t base, size_t size, int direction)
|
|
{
|
|
}
|
|
|
|
void sbus_dma_sync_sg_for_cpu(struct sbus_dev *sdev, struct scatterlist *sg, int nents, int direction)
|
|
{
|
|
struct sbus_iommu *iommu = sdev->bus->iommu;
|
|
unsigned long flags, size;
|
|
u32 base;
|
|
int i;
|
|
|
|
base = sg[0].dma_address & IO_PAGE_MASK;
|
|
for (i = 0; i < nents; i++) {
|
|
if (sg[i].dma_length == 0)
|
|
break;
|
|
}
|
|
i--;
|
|
size = IO_PAGE_ALIGN(sg[i].dma_address + sg[i].dma_length) - base;
|
|
|
|
spin_lock_irqsave(&iommu->lock, flags);
|
|
sbus_strbuf_flush(iommu, base, size >> IO_PAGE_SHIFT, direction);
|
|
spin_unlock_irqrestore(&iommu->lock, flags);
|
|
}
|
|
|
|
void sbus_dma_sync_sg_for_device(struct sbus_dev *sdev, struct scatterlist *sg, int nents, int direction)
|
|
{
|
|
}
|
|
|
|
/* Enable 64-bit DVMA mode for the given device. */
|
|
void sbus_set_sbus64(struct sbus_dev *sdev, int bursts)
|
|
{
|
|
struct sbus_iommu *iommu = sdev->bus->iommu;
|
|
int slot = sdev->slot;
|
|
unsigned long cfg_reg;
|
|
u64 val;
|
|
|
|
cfg_reg = iommu->sbus_control_reg;
|
|
switch (slot) {
|
|
case 0:
|
|
cfg_reg += 0x20UL;
|
|
break;
|
|
case 1:
|
|
cfg_reg += 0x28UL;
|
|
break;
|
|
case 2:
|
|
cfg_reg += 0x30UL;
|
|
break;
|
|
case 3:
|
|
cfg_reg += 0x38UL;
|
|
break;
|
|
case 13:
|
|
cfg_reg += 0x40UL;
|
|
break;
|
|
case 14:
|
|
cfg_reg += 0x48UL;
|
|
break;
|
|
case 15:
|
|
cfg_reg += 0x50UL;
|
|
break;
|
|
|
|
default:
|
|
return;
|
|
};
|
|
|
|
val = upa_readq(cfg_reg);
|
|
if (val & (1UL << 14UL)) {
|
|
/* Extended transfer mode already enabled. */
|
|
return;
|
|
}
|
|
|
|
val |= (1UL << 14UL);
|
|
|
|
if (bursts & DMA_BURST8)
|
|
val |= (1UL << 1UL);
|
|
if (bursts & DMA_BURST16)
|
|
val |= (1UL << 2UL);
|
|
if (bursts & DMA_BURST32)
|
|
val |= (1UL << 3UL);
|
|
if (bursts & DMA_BURST64)
|
|
val |= (1UL << 4UL);
|
|
upa_writeq(val, cfg_reg);
|
|
}
|
|
|
|
/* INO number to IMAP register offset for SYSIO external IRQ's.
|
|
* This should conform to both Sunfire/Wildfire server and Fusion
|
|
* desktop designs.
|
|
*/
|
|
#define SYSIO_IMAP_SLOT0 0x2c04UL
|
|
#define SYSIO_IMAP_SLOT1 0x2c0cUL
|
|
#define SYSIO_IMAP_SLOT2 0x2c14UL
|
|
#define SYSIO_IMAP_SLOT3 0x2c1cUL
|
|
#define SYSIO_IMAP_SCSI 0x3004UL
|
|
#define SYSIO_IMAP_ETH 0x300cUL
|
|
#define SYSIO_IMAP_BPP 0x3014UL
|
|
#define SYSIO_IMAP_AUDIO 0x301cUL
|
|
#define SYSIO_IMAP_PFAIL 0x3024UL
|
|
#define SYSIO_IMAP_KMS 0x302cUL
|
|
#define SYSIO_IMAP_FLPY 0x3034UL
|
|
#define SYSIO_IMAP_SHW 0x303cUL
|
|
#define SYSIO_IMAP_KBD 0x3044UL
|
|
#define SYSIO_IMAP_MS 0x304cUL
|
|
#define SYSIO_IMAP_SER 0x3054UL
|
|
#define SYSIO_IMAP_TIM0 0x3064UL
|
|
#define SYSIO_IMAP_TIM1 0x306cUL
|
|
#define SYSIO_IMAP_UE 0x3074UL
|
|
#define SYSIO_IMAP_CE 0x307cUL
|
|
#define SYSIO_IMAP_SBERR 0x3084UL
|
|
#define SYSIO_IMAP_PMGMT 0x308cUL
|
|
#define SYSIO_IMAP_GFX 0x3094UL
|
|
#define SYSIO_IMAP_EUPA 0x309cUL
|
|
|
|
#define bogon ((unsigned long) -1)
|
|
static unsigned long sysio_irq_offsets[] = {
|
|
/* SBUS Slot 0 --> 3, level 1 --> 7 */
|
|
SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
|
|
SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
|
|
SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
|
|
SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
|
|
SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
|
|
SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
|
|
SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
|
|
SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
|
|
|
|
/* Onboard devices (not relevant/used on SunFire). */
|
|
SYSIO_IMAP_SCSI,
|
|
SYSIO_IMAP_ETH,
|
|
SYSIO_IMAP_BPP,
|
|
bogon,
|
|
SYSIO_IMAP_AUDIO,
|
|
SYSIO_IMAP_PFAIL,
|
|
bogon,
|
|
bogon,
|
|
SYSIO_IMAP_KMS,
|
|
SYSIO_IMAP_FLPY,
|
|
SYSIO_IMAP_SHW,
|
|
SYSIO_IMAP_KBD,
|
|
SYSIO_IMAP_MS,
|
|
SYSIO_IMAP_SER,
|
|
bogon,
|
|
bogon,
|
|
SYSIO_IMAP_TIM0,
|
|
SYSIO_IMAP_TIM1,
|
|
bogon,
|
|
bogon,
|
|
SYSIO_IMAP_UE,
|
|
SYSIO_IMAP_CE,
|
|
SYSIO_IMAP_SBERR,
|
|
SYSIO_IMAP_PMGMT,
|
|
};
|
|
|
|
#undef bogon
|
|
|
|
#define NUM_SYSIO_OFFSETS ARRAY_SIZE(sysio_irq_offsets)
|
|
|
|
/* Convert Interrupt Mapping register pointer to associated
|
|
* Interrupt Clear register pointer, SYSIO specific version.
|
|
*/
|
|
#define SYSIO_ICLR_UNUSED0 0x3400UL
|
|
#define SYSIO_ICLR_SLOT0 0x340cUL
|
|
#define SYSIO_ICLR_SLOT1 0x344cUL
|
|
#define SYSIO_ICLR_SLOT2 0x348cUL
|
|
#define SYSIO_ICLR_SLOT3 0x34ccUL
|
|
static unsigned long sysio_imap_to_iclr(unsigned long imap)
|
|
{
|
|
unsigned long diff = SYSIO_ICLR_UNUSED0 - SYSIO_IMAP_SLOT0;
|
|
return imap + diff;
|
|
}
|
|
|
|
unsigned int sbus_build_irq(void *buscookie, unsigned int ino)
|
|
{
|
|
struct sbus_bus *sbus = (struct sbus_bus *)buscookie;
|
|
struct sbus_iommu *iommu = sbus->iommu;
|
|
unsigned long reg_base = iommu->sbus_control_reg - 0x2000UL;
|
|
unsigned long imap, iclr;
|
|
int sbus_level = 0;
|
|
|
|
imap = sysio_irq_offsets[ino];
|
|
if (imap == ((unsigned long)-1)) {
|
|
prom_printf("get_irq_translations: Bad SYSIO INO[%x]\n",
|
|
ino);
|
|
prom_halt();
|
|
}
|
|
imap += reg_base;
|
|
|
|
/* SYSIO inconsistency. For external SLOTS, we have to select
|
|
* the right ICLR register based upon the lower SBUS irq level
|
|
* bits.
|
|
*/
|
|
if (ino >= 0x20) {
|
|
iclr = sysio_imap_to_iclr(imap);
|
|
} else {
|
|
int sbus_slot = (ino & 0x18)>>3;
|
|
|
|
sbus_level = ino & 0x7;
|
|
|
|
switch(sbus_slot) {
|
|
case 0:
|
|
iclr = reg_base + SYSIO_ICLR_SLOT0;
|
|
break;
|
|
case 1:
|
|
iclr = reg_base + SYSIO_ICLR_SLOT1;
|
|
break;
|
|
case 2:
|
|
iclr = reg_base + SYSIO_ICLR_SLOT2;
|
|
break;
|
|
default:
|
|
case 3:
|
|
iclr = reg_base + SYSIO_ICLR_SLOT3;
|
|
break;
|
|
};
|
|
|
|
iclr += ((unsigned long)sbus_level - 1UL) * 8UL;
|
|
}
|
|
return build_irq(sbus_level, iclr, imap);
|
|
}
|
|
|
|
/* Error interrupt handling. */
|
|
#define SYSIO_UE_AFSR 0x0030UL
|
|
#define SYSIO_UE_AFAR 0x0038UL
|
|
#define SYSIO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO cause */
|
|
#define SYSIO_UEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read cause */
|
|
#define SYSIO_UEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write cause */
|
|
#define SYSIO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
|
|
#define SYSIO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read cause */
|
|
#define SYSIO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write cause*/
|
|
#define SYSIO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved */
|
|
#define SYSIO_UEAFSR_DOFF 0x0000e00000000000UL /* Doubleword Offset */
|
|
#define SYSIO_UEAFSR_SIZE 0x00001c0000000000UL /* Bad transfer size 2^SIZE */
|
|
#define SYSIO_UEAFSR_MID 0x000003e000000000UL /* UPA MID causing the fault */
|
|
#define SYSIO_UEAFSR_RESV2 0x0000001fffffffffUL /* Reserved */
|
|
static irqreturn_t sysio_ue_handler(int irq, void *dev_id, struct pt_regs *regs)
|
|
{
|
|
struct sbus_bus *sbus = dev_id;
|
|
struct sbus_iommu *iommu = sbus->iommu;
|
|
unsigned long reg_base = iommu->sbus_control_reg - 0x2000UL;
|
|
unsigned long afsr_reg, afar_reg;
|
|
unsigned long afsr, afar, error_bits;
|
|
int reported;
|
|
|
|
afsr_reg = reg_base + SYSIO_UE_AFSR;
|
|
afar_reg = reg_base + SYSIO_UE_AFAR;
|
|
|
|
/* Latch error status. */
|
|
afsr = upa_readq(afsr_reg);
|
|
afar = upa_readq(afar_reg);
|
|
|
|
/* Clear primary/secondary error status bits. */
|
|
error_bits = afsr &
|
|
(SYSIO_UEAFSR_PPIO | SYSIO_UEAFSR_PDRD | SYSIO_UEAFSR_PDWR |
|
|
SYSIO_UEAFSR_SPIO | SYSIO_UEAFSR_SDRD | SYSIO_UEAFSR_SDWR);
|
|
upa_writeq(error_bits, afsr_reg);
|
|
|
|
/* Log the error. */
|
|
printk("SYSIO[%x]: Uncorrectable ECC Error, primary error type[%s]\n",
|
|
sbus->portid,
|
|
(((error_bits & SYSIO_UEAFSR_PPIO) ?
|
|
"PIO" :
|
|
((error_bits & SYSIO_UEAFSR_PDRD) ?
|
|
"DVMA Read" :
|
|
((error_bits & SYSIO_UEAFSR_PDWR) ?
|
|
"DVMA Write" : "???")))));
|
|
printk("SYSIO[%x]: DOFF[%lx] SIZE[%lx] MID[%lx]\n",
|
|
sbus->portid,
|
|
(afsr & SYSIO_UEAFSR_DOFF) >> 45UL,
|
|
(afsr & SYSIO_UEAFSR_SIZE) >> 42UL,
|
|
(afsr & SYSIO_UEAFSR_MID) >> 37UL);
|
|
printk("SYSIO[%x]: AFAR[%016lx]\n", sbus->portid, afar);
|
|
printk("SYSIO[%x]: Secondary UE errors [", sbus->portid);
|
|
reported = 0;
|
|
if (afsr & SYSIO_UEAFSR_SPIO) {
|
|
reported++;
|
|
printk("(PIO)");
|
|
}
|
|
if (afsr & SYSIO_UEAFSR_SDRD) {
|
|
reported++;
|
|
printk("(DVMA Read)");
|
|
}
|
|
if (afsr & SYSIO_UEAFSR_SDWR) {
|
|
reported++;
|
|
printk("(DVMA Write)");
|
|
}
|
|
if (!reported)
|
|
printk("(none)");
|
|
printk("]\n");
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
#define SYSIO_CE_AFSR 0x0040UL
|
|
#define SYSIO_CE_AFAR 0x0048UL
|
|
#define SYSIO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO cause */
|
|
#define SYSIO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read cause */
|
|
#define SYSIO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write cause */
|
|
#define SYSIO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO cause */
|
|
#define SYSIO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read cause */
|
|
#define SYSIO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write cause*/
|
|
#define SYSIO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved */
|
|
#define SYSIO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits */
|
|
#define SYSIO_CEAFSR_DOFF 0x0000e00000000000UL /* Double Offset */
|
|
#define SYSIO_CEAFSR_SIZE 0x00001c0000000000UL /* Bad transfer size 2^SIZE */
|
|
#define SYSIO_CEAFSR_MID 0x000003e000000000UL /* UPA MID causing the fault */
|
|
#define SYSIO_CEAFSR_RESV2 0x0000001fffffffffUL /* Reserved */
|
|
static irqreturn_t sysio_ce_handler(int irq, void *dev_id, struct pt_regs *regs)
|
|
{
|
|
struct sbus_bus *sbus = dev_id;
|
|
struct sbus_iommu *iommu = sbus->iommu;
|
|
unsigned long reg_base = iommu->sbus_control_reg - 0x2000UL;
|
|
unsigned long afsr_reg, afar_reg;
|
|
unsigned long afsr, afar, error_bits;
|
|
int reported;
|
|
|
|
afsr_reg = reg_base + SYSIO_CE_AFSR;
|
|
afar_reg = reg_base + SYSIO_CE_AFAR;
|
|
|
|
/* Latch error status. */
|
|
afsr = upa_readq(afsr_reg);
|
|
afar = upa_readq(afar_reg);
|
|
|
|
/* Clear primary/secondary error status bits. */
|
|
error_bits = afsr &
|
|
(SYSIO_CEAFSR_PPIO | SYSIO_CEAFSR_PDRD | SYSIO_CEAFSR_PDWR |
|
|
SYSIO_CEAFSR_SPIO | SYSIO_CEAFSR_SDRD | SYSIO_CEAFSR_SDWR);
|
|
upa_writeq(error_bits, afsr_reg);
|
|
|
|
printk("SYSIO[%x]: Correctable ECC Error, primary error type[%s]\n",
|
|
sbus->portid,
|
|
(((error_bits & SYSIO_CEAFSR_PPIO) ?
|
|
"PIO" :
|
|
((error_bits & SYSIO_CEAFSR_PDRD) ?
|
|
"DVMA Read" :
|
|
((error_bits & SYSIO_CEAFSR_PDWR) ?
|
|
"DVMA Write" : "???")))));
|
|
|
|
/* XXX Use syndrome and afar to print out module string just like
|
|
* XXX UDB CE trap handler does... -DaveM
|
|
*/
|
|
printk("SYSIO[%x]: DOFF[%lx] ECC Syndrome[%lx] Size[%lx] MID[%lx]\n",
|
|
sbus->portid,
|
|
(afsr & SYSIO_CEAFSR_DOFF) >> 45UL,
|
|
(afsr & SYSIO_CEAFSR_ESYND) >> 48UL,
|
|
(afsr & SYSIO_CEAFSR_SIZE) >> 42UL,
|
|
(afsr & SYSIO_CEAFSR_MID) >> 37UL);
|
|
printk("SYSIO[%x]: AFAR[%016lx]\n", sbus->portid, afar);
|
|
|
|
printk("SYSIO[%x]: Secondary CE errors [", sbus->portid);
|
|
reported = 0;
|
|
if (afsr & SYSIO_CEAFSR_SPIO) {
|
|
reported++;
|
|
printk("(PIO)");
|
|
}
|
|
if (afsr & SYSIO_CEAFSR_SDRD) {
|
|
reported++;
|
|
printk("(DVMA Read)");
|
|
}
|
|
if (afsr & SYSIO_CEAFSR_SDWR) {
|
|
reported++;
|
|
printk("(DVMA Write)");
|
|
}
|
|
if (!reported)
|
|
printk("(none)");
|
|
printk("]\n");
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
#define SYSIO_SBUS_AFSR 0x2010UL
|
|
#define SYSIO_SBUS_AFAR 0x2018UL
|
|
#define SYSIO_SBAFSR_PLE 0x8000000000000000UL /* Primary Late PIO Error */
|
|
#define SYSIO_SBAFSR_PTO 0x4000000000000000UL /* Primary SBUS Timeout */
|
|
#define SYSIO_SBAFSR_PBERR 0x2000000000000000UL /* Primary SBUS Error ACK */
|
|
#define SYSIO_SBAFSR_SLE 0x1000000000000000UL /* Secondary Late PIO Error */
|
|
#define SYSIO_SBAFSR_STO 0x0800000000000000UL /* Secondary SBUS Timeout */
|
|
#define SYSIO_SBAFSR_SBERR 0x0400000000000000UL /* Secondary SBUS Error ACK */
|
|
#define SYSIO_SBAFSR_RESV1 0x03ff000000000000UL /* Reserved */
|
|
#define SYSIO_SBAFSR_RD 0x0000800000000000UL /* Primary was late PIO read */
|
|
#define SYSIO_SBAFSR_RESV2 0x0000600000000000UL /* Reserved */
|
|
#define SYSIO_SBAFSR_SIZE 0x00001c0000000000UL /* Size of transfer */
|
|
#define SYSIO_SBAFSR_MID 0x000003e000000000UL /* MID causing the error */
|
|
#define SYSIO_SBAFSR_RESV3 0x0000001fffffffffUL /* Reserved */
|
|
static irqreturn_t sysio_sbus_error_handler(int irq, void *dev_id, struct pt_regs *regs)
|
|
{
|
|
struct sbus_bus *sbus = dev_id;
|
|
struct sbus_iommu *iommu = sbus->iommu;
|
|
unsigned long afsr_reg, afar_reg, reg_base;
|
|
unsigned long afsr, afar, error_bits;
|
|
int reported;
|
|
|
|
reg_base = iommu->sbus_control_reg - 0x2000UL;
|
|
afsr_reg = reg_base + SYSIO_SBUS_AFSR;
|
|
afar_reg = reg_base + SYSIO_SBUS_AFAR;
|
|
|
|
afsr = upa_readq(afsr_reg);
|
|
afar = upa_readq(afar_reg);
|
|
|
|
/* Clear primary/secondary error status bits. */
|
|
error_bits = afsr &
|
|
(SYSIO_SBAFSR_PLE | SYSIO_SBAFSR_PTO | SYSIO_SBAFSR_PBERR |
|
|
SYSIO_SBAFSR_SLE | SYSIO_SBAFSR_STO | SYSIO_SBAFSR_SBERR);
|
|
upa_writeq(error_bits, afsr_reg);
|
|
|
|
/* Log the error. */
|
|
printk("SYSIO[%x]: SBUS Error, primary error type[%s] read(%d)\n",
|
|
sbus->portid,
|
|
(((error_bits & SYSIO_SBAFSR_PLE) ?
|
|
"Late PIO Error" :
|
|
((error_bits & SYSIO_SBAFSR_PTO) ?
|
|
"Time Out" :
|
|
((error_bits & SYSIO_SBAFSR_PBERR) ?
|
|
"Error Ack" : "???")))),
|
|
(afsr & SYSIO_SBAFSR_RD) ? 1 : 0);
|
|
printk("SYSIO[%x]: size[%lx] MID[%lx]\n",
|
|
sbus->portid,
|
|
(afsr & SYSIO_SBAFSR_SIZE) >> 42UL,
|
|
(afsr & SYSIO_SBAFSR_MID) >> 37UL);
|
|
printk("SYSIO[%x]: AFAR[%016lx]\n", sbus->portid, afar);
|
|
printk("SYSIO[%x]: Secondary SBUS errors [", sbus->portid);
|
|
reported = 0;
|
|
if (afsr & SYSIO_SBAFSR_SLE) {
|
|
reported++;
|
|
printk("(Late PIO Error)");
|
|
}
|
|
if (afsr & SYSIO_SBAFSR_STO) {
|
|
reported++;
|
|
printk("(Time Out)");
|
|
}
|
|
if (afsr & SYSIO_SBAFSR_SBERR) {
|
|
reported++;
|
|
printk("(Error Ack)");
|
|
}
|
|
if (!reported)
|
|
printk("(none)");
|
|
printk("]\n");
|
|
|
|
/* XXX check iommu/strbuf for further error status XXX */
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
#define ECC_CONTROL 0x0020UL
|
|
#define SYSIO_ECNTRL_ECCEN 0x8000000000000000UL /* Enable ECC Checking */
|
|
#define SYSIO_ECNTRL_UEEN 0x4000000000000000UL /* Enable UE Interrupts */
|
|
#define SYSIO_ECNTRL_CEEN 0x2000000000000000UL /* Enable CE Interrupts */
|
|
|
|
#define SYSIO_UE_INO 0x34
|
|
#define SYSIO_CE_INO 0x35
|
|
#define SYSIO_SBUSERR_INO 0x36
|
|
|
|
static void __init sysio_register_error_handlers(struct sbus_bus *sbus)
|
|
{
|
|
struct sbus_iommu *iommu = sbus->iommu;
|
|
unsigned long reg_base = iommu->sbus_control_reg - 0x2000UL;
|
|
unsigned int irq;
|
|
u64 control;
|
|
|
|
irq = sbus_build_irq(sbus, SYSIO_UE_INO);
|
|
if (request_irq(irq, sysio_ue_handler,
|
|
SA_SHIRQ, "SYSIO UE", sbus) < 0) {
|
|
prom_printf("SYSIO[%x]: Cannot register UE interrupt.\n",
|
|
sbus->portid);
|
|
prom_halt();
|
|
}
|
|
|
|
irq = sbus_build_irq(sbus, SYSIO_CE_INO);
|
|
if (request_irq(irq, sysio_ce_handler,
|
|
SA_SHIRQ, "SYSIO CE", sbus) < 0) {
|
|
prom_printf("SYSIO[%x]: Cannot register CE interrupt.\n",
|
|
sbus->portid);
|
|
prom_halt();
|
|
}
|
|
|
|
irq = sbus_build_irq(sbus, SYSIO_SBUSERR_INO);
|
|
if (request_irq(irq, sysio_sbus_error_handler,
|
|
SA_SHIRQ, "SYSIO SBUS Error", sbus) < 0) {
|
|
prom_printf("SYSIO[%x]: Cannot register SBUS Error interrupt.\n",
|
|
sbus->portid);
|
|
prom_halt();
|
|
}
|
|
|
|
/* Now turn the error interrupts on and also enable ECC checking. */
|
|
upa_writeq((SYSIO_ECNTRL_ECCEN |
|
|
SYSIO_ECNTRL_UEEN |
|
|
SYSIO_ECNTRL_CEEN),
|
|
reg_base + ECC_CONTROL);
|
|
|
|
control = upa_readq(iommu->sbus_control_reg);
|
|
control |= 0x100UL; /* SBUS Error Interrupt Enable */
|
|
upa_writeq(control, iommu->sbus_control_reg);
|
|
}
|
|
|
|
/* Boot time initialization. */
|
|
static void __init sbus_iommu_init(int __node, struct sbus_bus *sbus)
|
|
{
|
|
struct linux_prom64_registers *pr;
|
|
struct device_node *dp;
|
|
struct sbus_iommu *iommu;
|
|
unsigned long regs, tsb_base;
|
|
u64 control;
|
|
int i;
|
|
|
|
dp = of_find_node_by_phandle(__node);
|
|
|
|
sbus->portid = of_getintprop_default(dp, "upa-portid", -1);
|
|
|
|
pr = of_get_property(dp, "reg", NULL);
|
|
if (!pr) {
|
|
prom_printf("sbus_iommu_init: Cannot map SYSIO control registers.\n");
|
|
prom_halt();
|
|
}
|
|
regs = pr->phys_addr;
|
|
|
|
iommu = kmalloc(sizeof(*iommu) + SMP_CACHE_BYTES, GFP_ATOMIC);
|
|
if (iommu == NULL) {
|
|
prom_printf("sbus_iommu_init: Fatal error, kmalloc(iommu) failed\n");
|
|
prom_halt();
|
|
}
|
|
|
|
/* Align on E$ line boundary. */
|
|
iommu = (struct sbus_iommu *)
|
|
(((unsigned long)iommu + (SMP_CACHE_BYTES - 1UL)) &
|
|
~(SMP_CACHE_BYTES - 1UL));
|
|
|
|
memset(iommu, 0, sizeof(*iommu));
|
|
|
|
/* We start with no consistent mappings. */
|
|
iommu->lowest_consistent_map = CLUSTER_NPAGES;
|
|
|
|
for (i = 0; i < NCLUSTERS; i++) {
|
|
iommu->alloc_info[i].flush = 0;
|
|
iommu->alloc_info[i].next = 0;
|
|
}
|
|
|
|
/* Setup spinlock. */
|
|
spin_lock_init(&iommu->lock);
|
|
|
|
/* Init register offsets. */
|
|
iommu->iommu_regs = regs + SYSIO_IOMMUREG_BASE;
|
|
iommu->strbuf_regs = regs + SYSIO_STRBUFREG_BASE;
|
|
|
|
/* The SYSIO SBUS control register is used for dummy reads
|
|
* in order to ensure write completion.
|
|
*/
|
|
iommu->sbus_control_reg = regs + 0x2000UL;
|
|
|
|
/* Link into SYSIO software state. */
|
|
sbus->iommu = iommu;
|
|
|
|
printk("SYSIO: UPA portID %x, at %016lx\n",
|
|
sbus->portid, regs);
|
|
|
|
/* Setup for TSB_SIZE=7, TBW_SIZE=0, MMU_DE=1, MMU_EN=1 */
|
|
control = upa_readq(iommu->iommu_regs + IOMMU_CONTROL);
|
|
control = ((7UL << 16UL) |
|
|
(0UL << 2UL) |
|
|
(1UL << 1UL) |
|
|
(1UL << 0UL));
|
|
|
|
/* Using the above configuration we need 1MB iommu page
|
|
* table (128K ioptes * 8 bytes per iopte). This is
|
|
* page order 7 on UltraSparc.
|
|
*/
|
|
tsb_base = __get_free_pages(GFP_ATOMIC, get_order(IO_TSB_SIZE));
|
|
if (tsb_base == 0UL) {
|
|
prom_printf("sbus_iommu_init: Fatal error, cannot alloc TSB table.\n");
|
|
prom_halt();
|
|
}
|
|
|
|
iommu->page_table = (iopte_t *) tsb_base;
|
|
memset(iommu->page_table, 0, IO_TSB_SIZE);
|
|
|
|
upa_writeq(control, iommu->iommu_regs + IOMMU_CONTROL);
|
|
|
|
/* Clean out any cruft in the IOMMU using
|
|
* diagnostic accesses.
|
|
*/
|
|
for (i = 0; i < 16; i++) {
|
|
unsigned long dram = iommu->iommu_regs + IOMMU_DRAMDIAG;
|
|
unsigned long tag = iommu->iommu_regs + IOMMU_TAGDIAG;
|
|
|
|
dram += (unsigned long)i * 8UL;
|
|
tag += (unsigned long)i * 8UL;
|
|
upa_writeq(0, dram);
|
|
upa_writeq(0, tag);
|
|
}
|
|
upa_readq(iommu->sbus_control_reg);
|
|
|
|
/* Give the TSB to SYSIO. */
|
|
upa_writeq(__pa(tsb_base), iommu->iommu_regs + IOMMU_TSBBASE);
|
|
|
|
/* Setup streaming buffer, DE=1 SB_EN=1 */
|
|
control = (1UL << 1UL) | (1UL << 0UL);
|
|
upa_writeq(control, iommu->strbuf_regs + STRBUF_CONTROL);
|
|
|
|
/* Clear out the tags using diagnostics. */
|
|
for (i = 0; i < 16; i++) {
|
|
unsigned long ptag, ltag;
|
|
|
|
ptag = iommu->strbuf_regs + STRBUF_PTAGDIAG;
|
|
ltag = iommu->strbuf_regs + STRBUF_LTAGDIAG;
|
|
ptag += (unsigned long)i * 8UL;
|
|
ltag += (unsigned long)i * 8UL;
|
|
|
|
upa_writeq(0UL, ptag);
|
|
upa_writeq(0UL, ltag);
|
|
}
|
|
|
|
/* Enable DVMA arbitration for all devices/slots. */
|
|
control = upa_readq(iommu->sbus_control_reg);
|
|
control |= 0x3fUL;
|
|
upa_writeq(control, iommu->sbus_control_reg);
|
|
|
|
/* Now some Xfire specific grot... */
|
|
if (this_is_starfire)
|
|
starfire_hookup(sbus->portid);
|
|
|
|
sysio_register_error_handlers(sbus);
|
|
}
|
|
|
|
void sbus_fill_device_irq(struct sbus_dev *sdev)
|
|
{
|
|
struct device_node *dp = of_find_node_by_phandle(sdev->prom_node);
|
|
struct linux_prom_irqs *irqs;
|
|
|
|
irqs = of_get_property(dp, "interrupts", NULL);
|
|
if (!irqs) {
|
|
sdev->irqs[0] = 0;
|
|
sdev->num_irqs = 0;
|
|
} else {
|
|
unsigned int pri = irqs[0].pri;
|
|
|
|
sdev->num_irqs = 1;
|
|
if (pri < 0x20)
|
|
pri += sdev->slot * 8;
|
|
|
|
sdev->irqs[0] = sbus_build_irq(sdev->bus, pri);
|
|
}
|
|
}
|
|
|
|
void __init sbus_arch_bus_ranges_init(struct device_node *pn, struct sbus_bus *sbus)
|
|
{
|
|
}
|
|
|
|
void __init sbus_setup_iommu(struct sbus_bus *sbus, struct device_node *dp)
|
|
{
|
|
sbus_iommu_init(dp->node, sbus);
|
|
}
|
|
|
|
void __init sbus_setup_arch_props(struct sbus_bus *sbus, struct device_node *dp)
|
|
{
|
|
}
|
|
|
|
int __init sbus_arch_preinit(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
void __init sbus_arch_postinit(void)
|
|
{
|
|
extern void firetruck_init(void);
|
|
|
|
firetruck_init();
|
|
}
|