forked from Minki/linux
bed80507e1
Add common DT bindings to support PCI controller driver for port 0 on all of the K2 SoCs that has Synopsis Designware based pcie h/w. Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
335 lines
8.7 KiB
Plaintext
335 lines
8.7 KiB
Plaintext
/*
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* Copyright 2013 Texas Instruments, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/gpio/gpio.h>
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#include "skeleton.dtsi"
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/ {
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model = "Texas Instruments Keystone 2 SoC";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&gic>;
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aliases {
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serial0 = &uart0;
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};
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memory {
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reg = <0x00000000 0x80000000 0x00000000 0x40000000>;
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};
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gic: interrupt-controller {
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compatible = "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x0 0x02561000 0x0 0x1000>,
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<0x0 0x02562000 0x0 0x2000>,
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<0x0 0x02564000 0x0 0x1000>,
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<0x0 0x02566000 0x0 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_HIGH)>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts =
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<GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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};
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pmu {
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compatible = "arm,cortex-a15-pmu";
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interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 23 IRQ_TYPE_EDGE_RISING>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "ti,keystone","simple-bus";
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interrupt-parent = <&gic>;
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ranges = <0x0 0x0 0x0 0xc0000000>;
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dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>;
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pllctrl: pll-controller@02310000 {
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compatible = "ti,keystone-pllctrl", "syscon";
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reg = <0x02310000 0x200>;
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};
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devctrl: device-state-control@02620000 {
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compatible = "ti,keystone-devctrl", "syscon";
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reg = <0x02620000 0x1000>;
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};
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rstctrl: reset-controller {
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compatible = "ti,keystone-reset";
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ti,syscon-pll = <&pllctrl 0xe4>;
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ti,syscon-dev = <&devctrl 0x328>;
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ti,wdt-list = <0>;
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};
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/include/ "keystone-clocks.dtsi"
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uart0: serial@02530c00 {
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compatible = "ns16550a";
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current-speed = <115200>;
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reg-shift = <2>;
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reg-io-width = <4>;
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reg = <0x02530c00 0x100>;
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clocks = <&clkuart0>;
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interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
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};
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uart1: serial@02531000 {
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compatible = "ns16550a";
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current-speed = <115200>;
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reg-shift = <2>;
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reg-io-width = <4>;
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reg = <0x02531000 0x100>;
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clocks = <&clkuart1>;
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interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
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};
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i2c0: i2c@2530000 {
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compatible = "ti,davinci-i2c";
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reg = <0x02530000 0x400>;
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clock-frequency = <100000>;
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clocks = <&clki2c>;
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interrupts = <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c1: i2c@2530400 {
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compatible = "ti,davinci-i2c";
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reg = <0x02530400 0x400>;
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clock-frequency = <100000>;
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clocks = <&clki2c>;
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interrupts = <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c2: i2c@2530800 {
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compatible = "ti,davinci-i2c";
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reg = <0x02530800 0x400>;
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clock-frequency = <100000>;
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clocks = <&clki2c>;
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interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spi0: spi@21000400 {
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compatible = "ti,dm6441-spi";
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reg = <0x21000400 0x200>;
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num-cs = <4>;
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ti,davinci-spi-intr-line = <0>;
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interrupts = <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>;
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clocks = <&clkspi>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spi1: spi@21000600 {
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compatible = "ti,dm6441-spi";
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reg = <0x21000600 0x200>;
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num-cs = <4>;
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ti,davinci-spi-intr-line = <0>;
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interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>;
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clocks = <&clkspi>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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spi2: spi@21000800 {
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compatible = "ti,dm6441-spi";
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reg = <0x21000800 0x200>;
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num-cs = <4>;
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ti,davinci-spi-intr-line = <0>;
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interrupts = <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>;
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clocks = <&clkspi>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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usb_phy: usb_phy@2620738 {
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compatible = "ti,keystone-usbphy";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x2620738 24>;
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status = "disabled";
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};
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usb: usb@2680000 {
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compatible = "ti,keystone-dwc3";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x2680000 0x10000>;
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clocks = <&clkusb>;
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clock-names = "usb";
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interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
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ranges;
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dma-coherent;
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dma-ranges;
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status = "disabled";
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dwc3@2690000 {
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compatible = "synopsys,dwc3";
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reg = <0x2690000 0x70000>;
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interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
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usb-phy = <&usb_phy>, <&usb_phy>;
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};
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};
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wdt: wdt@022f0080 {
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compatible = "ti,keystone-wdt","ti,davinci-wdt";
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reg = <0x022f0080 0x80>;
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clocks = <&clkwdtimer0>;
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};
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clock_event: timer@22f0000 {
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compatible = "ti,keystone-timer";
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reg = <0x022f0000 0x80>;
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interrupts = <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>;
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clocks = <&clktimer15>;
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};
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gpio0: gpio@260bf00 {
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compatible = "ti,keystone-gpio";
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reg = <0x0260bf00 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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/* HW Interrupts mapped to GPIO pins */
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interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 121 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 123 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 124 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 142 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 143 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 144 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 146 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 147 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 148 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 150 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 151 IRQ_TYPE_EDGE_RISING>;
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clocks = <&clkgpio>;
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clock-names = "gpio";
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ti,ngpio = <32>;
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ti,davinci-gpio-unbanked = <32>;
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};
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aemif: aemif@21000A00 {
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compatible = "ti,keystone-aemif", "ti,davinci-aemif";
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#address-cells = <2>;
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#size-cells = <1>;
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clocks = <&clkaemif>;
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clock-names = "aemif";
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clock-ranges;
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reg = <0x21000A00 0x00000100>;
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ranges = <0 0 0x30000000 0x10000000
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1 0 0x21000A00 0x00000100>;
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};
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mdio: mdio@02090300 {
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compatible = "ti,keystone_mdio", "ti,davinci_mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x02090300 0x100>;
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status = "disabled";
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clocks = <&clkpa>;
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clock-names = "fck";
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bus_freq = <2500000>;
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};
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kirq0: keystone_irq@26202a0 {
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compatible = "ti,keystone-irq";
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interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
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interrupt-controller;
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#interrupt-cells = <1>;
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ti,syscon-dev = <&devctrl 0x2a0>;
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};
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pcie@21800000 {
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compatible = "ti,keystone-pcie", "snps,dw-pcie";
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clocks = <&clkpcie>;
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clock-names = "pcie";
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#address-cells = <3>;
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#size-cells = <2>;
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reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>;
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ranges = <0x81000000 0 0 0x23250000 0 0x4000
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0x82000000 0 0x50000000 0x50000000 0 0x10000000>;
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device_type = "pci";
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num-lanes = <2>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */
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<0 0 0 2 &pcie_intc0 1>, /* INT B */
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<0 0 0 3 &pcie_intc0 2>, /* INT C */
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<0 0 0 4 &pcie_intc0 3>; /* INT D */
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pcie_msi_intc0: msi-interrupt-controller {
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
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};
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pcie_intc0: legacy-interrupt-controller {
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
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};
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};
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};
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};
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