forked from Minki/linux
9246e7ff24
This patch adds new exynos4415.dtsi to support Exynos4415 SoC based on Cortex-A9 quad cores and includes following dt nodes: - GIC interrupt controller (GIC-400) - Pinctrl to control three GPIO parts - CMU (Clock Management Unit) for CMU/CMU_DMC/AUDSS - CPU information (Cortex-A9 quad cores) - UART to support serial port - MCT (Multi Core Timer) - ADC (Analog Digital Converter) - RTC (Real Time Clock) - I2C/SPI busses - Power domains (CAM, TV, MFC, G3D, LCD0, ISP0/1) - PMU (Performance Monitoring Unit) - MSHC (Mobile Storage Host Controller) - EHCI (Enhanced Host Controller Interface) - OHIC (Open Host Controller Interface) - USB 2.0 device with hsotg - PWM (Pluse Width Modulation) Timer - AMBA bus for PDMA0/1 - SYSRAM node for memory mapping - SYSREG node for memory mapping - PMU (Power Management Unit) node for memory mapping Cc: Ben Dooks <ben-linux@fluff.org> Cc: Russell King <linux@arm.linux.org.uk> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Olof Johansson <olof@lixom.net> Cc: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com> [m.szyprowski: Add OHCI node and correct EHCI node] Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> [yj44.cho: Add mipi-phy node] Signed-off-by: YoungJun Cho <yj44.cho@samsung.com> [jaewon02: Add EHCI and SPI_2 node] Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> [ideal.song: Add I2S0 node for audio interface] Signed-off-by: Inha Song <ideal.song@samsung.com> [tomasz.figa: Add L2 cache node] Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
605 lines
14 KiB
Plaintext
605 lines
14 KiB
Plaintext
/*
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* Samsung's Exynos4415 SoC device tree source
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*
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* Copyright (c) 2014 Samsung Electronics Co., Ltd.
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*
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* Samsung's Exynos4415 SoC device nodes are listed in this file. Exynos4415
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* based board files can include this file and provide values for board
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* specific bindings.
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*
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* Note: This file does not include device nodes for all the controllers in
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* Exynos4415 SoC. As device tree coverage for Exynos4415 increases, additional
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* nodes can be added to this file.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/clock/exynos4415.h>
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#include <dt-bindings/clock/exynos-audss-clk.h>
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/ {
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compatible = "samsung,exynos4415";
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interrupt-parent = <&gic>;
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aliases {
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pinctrl0 = &pinctrl_0;
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pinctrl1 = &pinctrl_1;
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pinctrl2 = &pinctrl_2;
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mshc0 = &mshc_0;
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mshc1 = &mshc_1;
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mshc2 = &mshc_2;
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spi0 = &spi_0;
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spi1 = &spi_1;
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spi2 = &spi_2;
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i2c0 = &i2c_0;
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i2c1 = &i2c_1;
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i2c2 = &i2c_2;
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i2c3 = &i2c_3;
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i2c4 = &i2c_4;
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i2c5 = &i2c_5;
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i2c6 = &i2c_6;
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i2c7 = &i2c_7;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@a00 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0xa00>;
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clock-frequency = <1600000000>;
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};
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cpu1: cpu@a01 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0xa01>;
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clock-frequency = <1600000000>;
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};
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cpu2: cpu@a02 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0xa02>;
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clock-frequency = <1600000000>;
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};
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cpu3: cpu@a03 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0xa03>;
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clock-frequency = <1600000000>;
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};
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};
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soc: soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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sysram@02020000 {
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compatible = "mmio-sram";
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reg = <0x02020000 0x50000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x02020000 0x50000>;
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smp-sysram@0 {
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compatible = "samsung,exynos4210-sysram";
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reg = <0x0 0x1000>;
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};
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smp-sysram@4f000 {
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compatible = "samsung,exynos4210-sysram-ns";
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reg = <0x4f000 0x1000>;
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};
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};
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pinctrl_2: pinctrl@03860000 {
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compatible = "samsung,exynos4415-pinctrl";
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reg = <0x03860000 0x1000>;
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interrupts = <0 242 0>;
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};
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chipid@10000000 {
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compatible = "samsung,exynos4210-chipid";
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reg = <0x10000000 0x100>;
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};
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sysreg_system_controller: syscon@10010000 {
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compatible = "samsung,exynos4-sysreg", "syscon";
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reg = <0x10010000 0x400>;
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};
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pmu_system_controller: system-controller@10020000 {
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compatible = "samsung,exynos4415-pmu", "syscon";
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reg = <0x10020000 0x4000>;
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};
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mipi_phy: video-phy@10020710 {
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compatible = "samsung,s5pv210-mipi-video-phy";
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reg = <0x10020710 8>;
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#phy-cells = <1>;
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};
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pd_cam: cam-power-domain@10024000 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10024000 0x20>;
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};
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pd_tv: tv-power-domain@10024020 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10024020 0x20>;
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};
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pd_mfc: mfc-power-domain@10024040 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10024040 0x20>;
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};
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pd_g3d: g3d-power-domain@10024060 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10024060 0x20>;
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};
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pd_lcd0: lcd0-power-domain@10024080 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x10024080 0x20>;
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};
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pd_isp0: isp0-power-domain@100240A0 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x100240A0 0x20>;
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};
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pd_isp1: isp1-power-domain@100240E0 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x100240E0 0x20>;
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};
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cmu: clock-controller@10030000 {
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compatible = "samsung,exynos4415-cmu";
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reg = <0x10030000 0x18000>;
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#clock-cells = <1>;
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};
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rtc: rtc@10070000 {
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compatible = "samsung,exynos3250-rtc";
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reg = <0x10070000 0x100>;
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interrupts = <0 73 0>, <0 74 0>;
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status = "disabled";
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};
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mct@10050000 {
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compatible = "samsung,exynos4210-mct";
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reg = <0x10050000 0x800>;
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interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
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<0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
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clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
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clock-names = "fin_pll", "mct";
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};
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gic: interrupt-controller@10481000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x10481000 0x1000>,
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<0x10482000 0x1000>,
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<0x10484000 0x2000>,
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<0x10486000 0x2000>;
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interrupts = <1 9 0xf04>;
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};
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l2c: l2-cache-controller@10502000 {
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compatible = "arm,pl310-cache";
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reg = <0x10502000 0x1000>;
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cache-unified;
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cache-level = <2>;
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arm,tag-latency = <2 2 1>;
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arm,data-latency = <3 2 1>;
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arm,double-linefill = <1>;
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arm,double-linefill-incr = <0>;
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arm,double-linefill-wrap = <1>;
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arm,prefetch-drop = <1>;
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arm,prefetch-offset = <7>;
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};
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cmu_dmc: clock-controller@105C0000 {
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compatible = "samsung,exynos4415-cmu-dmc";
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reg = <0x105C0000 0x3000>;
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#clock-cells = <1>;
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};
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pinctrl_1: pinctrl@11000000 {
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compatible = "samsung,exynos4415-pinctrl";
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reg = <0x11000000 0x1000>;
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interrupts = <0 225 0>;
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wakeup-interrupt-controller {
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compatible = "samsung,exynos4210-wakeup-eint";
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interrupt-parent = <&gic>;
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interrupts = <0 48 0>;
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};
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};
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pinctrl_0: pinctrl@11400000 {
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compatible = "samsung,exynos4415-pinctrl";
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reg = <0x11400000 0x1000>;
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interrupts = <0 240 0>;
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};
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hsotg: hsotg@12480000 {
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compatible = "samsung,s3c6400-hsotg";
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reg = <0x12480000 0x20000>;
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interrupts = <0 141 0>;
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clocks = <&cmu CLK_USBDEVICE>;
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clock-names = "otg";
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phys = <&exynos_usbphy 0>;
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phy-names = "usb2-phy";
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status = "disabled";
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};
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mshc_0: mshc@12510000 {
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compatible = "samsung,exynos5250-dw-mshc";
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reg = <0x12510000 0x1000>;
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interrupts = <0 142 0>;
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clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
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clock-names = "biu", "ciu";
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fifo-depth = <0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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mshc_1: mshc@12520000 {
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compatible = "samsung,exynos5250-dw-mshc";
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reg = <0x12520000 0x1000>;
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interrupts = <0 143 0>;
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clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
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clock-names = "biu", "ciu";
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fifo-depth = <0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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mshc_2: mshc@12530000 {
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compatible = "samsung,exynos5250-dw-mshc";
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reg = <0x12530000 0x1000>;
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interrupts = <0 144 0>;
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clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>;
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clock-names = "biu", "ciu";
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fifo-depth = <0x80>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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ehci: ehci@12580000 {
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compatible = "samsung,exynos4210-ehci";
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reg = <0x12580000 0x100>;
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interrupts = <0 140 0>;
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clocks = <&cmu CLK_USBHOST>;
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clock-names = "usbhost";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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phys = <&exynos_usbphy 1>;
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status = "disabled";
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};
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port@1 {
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reg = <1>;
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phys = <&exynos_usbphy 2>;
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status = "disabled";
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};
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port@2 {
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reg = <2>;
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phys = <&exynos_usbphy 3>;
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status = "disabled";
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};
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};
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ohci: ohci@12590000 {
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compatible = "samsung,exynos4210-ohci";
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reg = <0x12590000 0x100>;
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interrupts = <0 140 0>;
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clocks = <&cmu CLK_USBHOST>;
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clock-names = "usbhost";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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phys = <&exynos_usbphy 1>;
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status = "disabled";
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};
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};
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exynos_usbphy: exynos-usbphy@125B0000 {
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compatible = "samsung,exynos4x12-usb2-phy";
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reg = <0x125B0000 0x100>;
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samsung,pmureg-phandle = <&pmu_system_controller>;
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samsung,sysreg-phandle = <&sysreg_system_controller>;
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clocks = <&cmu CLK_USBDEVICE>, <&xusbxti>;
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clock-names = "phy", "ref";
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#phy-cells = <1>;
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status = "disabled";
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};
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amba {
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compatible = "arm,amba-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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ranges;
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pdma0: pdma@12680000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x12680000 0x1000>;
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interrupts = <0 138 0>;
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clocks = <&cmu CLK_PDMA0>;
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clock-names = "apb_pclk";
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#dma-cells = <1>;
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#dma-channels = <8>;
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#dma-requests = <32>;
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};
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pdma1: pdma@12690000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x12690000 0x1000>;
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interrupts = <0 139 0>;
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clocks = <&cmu CLK_PDMA1>;
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clock-names = "apb_pclk";
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#dma-cells = <1>;
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#dma-channels = <8>;
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#dma-requests = <32>;
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};
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};
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adc: adc@126C0000 {
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compatible = "samsung,exynos3250-adc",
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"samsung,exynos-adc-v2";
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reg = <0x126C0000 0x100>, <0x10020718 0x4>;
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interrupts = <0 137 0>;
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clock-names = "adc", "sclk";
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clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
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#io-channel-cells = <1>;
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io-channel-ranges;
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status = "disabled";
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};
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serial_0: serial@13800000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x13800000 0x100>;
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interrupts = <0 109 0>;
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clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
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clock-names = "uart", "clk_uart_baud0";
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status = "disabled";
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};
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serial_1: serial@13810000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x13810000 0x100>;
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interrupts = <0 110 0>;
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clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
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clock-names = "uart", "clk_uart_baud0";
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status = "disabled";
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};
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serial_2: serial@13820000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x13820000 0x100>;
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interrupts = <0 111 0>;
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clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>;
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clock-names = "uart", "clk_uart_baud0";
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status = "disabled";
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};
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serial_3: serial@13830000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x13830000 0x100>;
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interrupts = <0 112 0>;
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clocks = <&cmu CLK_UART3>, <&cmu CLK_SCLK_UART3>;
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clock-names = "uart", "clk_uart_baud0";
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status = "disabled";
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};
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i2c_0: i2c@13860000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "samsung,s3c2440-i2c";
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reg = <0x13860000 0x100>;
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interrupts = <0 113 0>;
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clocks = <&cmu CLK_I2C0>;
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clock-names = "i2c";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_bus>;
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status = "disabled";
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};
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i2c_1: i2c@13870000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "samsung,s3c2440-i2c";
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reg = <0x13870000 0x100>;
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interrupts = <0 114 0>;
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clocks = <&cmu CLK_I2C1>;
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clock-names = "i2c";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_bus>;
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status = "disabled";
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};
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i2c_2: i2c@13880000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "samsung,s3c2440-i2c";
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reg = <0x13880000 0x100>;
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interrupts = <0 115 0>;
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clocks = <&cmu CLK_I2C2>;
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clock-names = "i2c";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c2_bus>;
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status = "disabled";
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};
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i2c_3: i2c@13890000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "samsung,s3c2440-i2c";
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reg = <0x13890000 0x100>;
|
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interrupts = <0 116 0>;
|
|
clocks = <&cmu CLK_I2C3>;
|
|
clock-names = "i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c3_bus>;
|
|
status = "disabled";
|
|
};
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|
|
|
i2c_4: i2c@138A0000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "samsung,s3c2440-i2c";
|
|
reg = <0x138A0000 0x100>;
|
|
interrupts = <0 117 0>;
|
|
clocks = <&cmu CLK_I2C4>;
|
|
clock-names = "i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c4_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_5: i2c@138B0000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "samsung,s3c2440-i2c";
|
|
reg = <0x138B0000 0x100>;
|
|
interrupts = <0 118 0>;
|
|
clocks = <&cmu CLK_I2C5>;
|
|
clock-names = "i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c5_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_6: i2c@138C0000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "samsung,s3c2440-i2c";
|
|
reg = <0x138C0000 0x100>;
|
|
interrupts = <0 119 0>;
|
|
clocks = <&cmu CLK_I2C6>;
|
|
clock-names = "i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c6_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c_7: i2c@138D0000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "samsung,s3c2440-i2c";
|
|
reg = <0x138D0000 0x100>;
|
|
interrupts = <0 120 0>;
|
|
clocks = <&cmu CLK_I2C7>;
|
|
clock-names = "i2c";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2c7_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi_0: spi@13920000 {
|
|
compatible = "samsung,exynos4210-spi";
|
|
reg = <0x13920000 0x100>;
|
|
interrupts = <0 121 0>;
|
|
dmas = <&pdma0 7>, <&pdma0 6>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
|
|
clock-names = "spi", "spi_busclk0";
|
|
samsung,spi-src-clk = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi0_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi_1: spi@13930000 {
|
|
compatible = "samsung,exynos4210-spi";
|
|
reg = <0x13930000 0x100>;
|
|
interrupts = <0 122 0>;
|
|
dmas = <&pdma1 7>, <&pdma1 6>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
|
|
clock-names = "spi", "spi_busclk0";
|
|
samsung,spi-src-clk = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi1_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi_2: spi@13940000 {
|
|
compatible = "samsung,exynos4210-spi";
|
|
reg = <0x13940000 0x100>;
|
|
interrupts = <0 123 0>;
|
|
dmas = <&pdma0 9>, <&pdma0 8>;
|
|
dma-names = "tx", "rx";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&cmu CLK_SPI2>, <&cmu CLK_SCLK_SPI2>;
|
|
clock-names = "spi", "spi_busclk0";
|
|
samsung,spi-src-clk = <0>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&spi2_bus>;
|
|
status = "disabled";
|
|
};
|
|
|
|
clock_audss: clock-controller@03810000 {
|
|
compatible = "samsung,exynos4210-audss-clock";
|
|
reg = <0x03810000 0x0C>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
i2s0: i2s@3830000 {
|
|
compatible = "samsung,s5pv210-i2s";
|
|
reg = <0x03830000 0x100>;
|
|
interrupts = <0 124 0>;
|
|
clocks = <&clock_audss EXYNOS_I2S_BUS>,
|
|
<&clock_audss EXYNOS_SCLK_I2S>;
|
|
clock-names = "iis", "i2s_opclk0";
|
|
dmas = <&pdma1 10>, <&pdma1 9>, <&pdma1 8>;
|
|
dma-names = "tx", "rx", "tx-sec";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&i2s0_bus>;
|
|
samsung,idma-addr = <0x03000000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm: pwm@139D0000 {
|
|
compatible = "samsung,exynos4210-pwm";
|
|
reg = <0x139D0000 0x1000>;
|
|
interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
|
|
<0 107 0>, <0 108 0>;
|
|
#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pmu {
|
|
compatible = "arm,cortex-a9-pmu";
|
|
interrupts = <0 18 0>, <0 19 0>, <0 20 0>, <0 21 0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
#include "exynos4415-pinctrl.dtsi"
|