ADG inputs clock from CLK{A,B,C,I} and outputs clock from CLKOUT{0,1,2,3} which is selected by BRG{A,B}. Now, ADG is assuming BRGA is for 44100Hz related clocks, BRGB is for 48000Hz related clocks. Clock related debug is very difficult/confusable. This patch cleanups clock related debug info. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Mark Brown <broonie@kernel.org> |
||
---|---|---|
.. | ||
rcar | ||
dma-sh7760.c | ||
fsi.c | ||
hac.c | ||
Kconfig | ||
Makefile | ||
migor.c | ||
sh7760-ac97.c | ||
siu_dai.c | ||
siu_pcm.c | ||
siu.h | ||
ssi.c |