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67a82dbc0a
linux/drivers/gpu/host1x/hw
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Thierry Reding 67a82dbc0a gpu: host1x: Support 40-bit addressing 
Tegra186 and later support 40 bits of address space. Additional
registers need to be programmed to store the full 40 bits of push
buffer addresses.

Since command stream gathers can also reside in buffers in a 40-bit
address space, a new variant of the GATHER opcode is also introduced.
It takes two parameters: the first parameter contains the lower 32
bits of the address and the second parameter contains bits 32 to 39.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2019-02-07 18:28:35 +01:00
..
cdma_hw.c gpu: host1x: Support 40-bit addressing 2019-02-07 18:28:35 +01:00
channel_hw.c gpu: host1x: Support 40-bit addressing 2019-02-07 18:28:35 +01:00
debug_hw_1x01.c gpu: host1x: Disassemble more instructions 2017-10-20 14:19:52 +02:00
debug_hw_1x06.c gpu: host1x: Add Tegra194 support 2018-11-29 17:11:49 +01:00
debug_hw.c gpu: host1x: Disassemble more instructions 2017-10-20 14:19:52 +02:00
host1x01_hardware.h
host1x01.c gpu: host1x: Add Tegra186 support 2017-10-20 14:19:51 +02:00
host1x01.h
host1x02_hardware.h
host1x02.c gpu: host1x: Add Tegra186 support 2017-10-20 14:19:51 +02:00
host1x02.h
host1x04_hardware.h
host1x04.c gpu: host1x: Add Tegra186 support 2017-10-20 14:19:51 +02:00
host1x04.h
host1x05_hardware.h gpu: host1x: Add Tegra210 support 2015-12-14 10:50:33 +01:00
host1x05.c gpu: host1x: Add Tegra186 support 2017-10-20 14:19:51 +02:00
host1x05.h gpu: host1x: Add Tegra210 support 2015-12-14 10:50:33 +01:00
host1x06_hardware.h gpu: host1x: Support 40-bit addressing 2019-02-07 18:28:35 +01:00
host1x06.c gpu: host1x: Add Tegra186 support 2017-10-20 14:19:51 +02:00
host1x06.h gpu: host1x: Add Tegra186 support 2017-10-20 14:19:51 +02:00
host1x07_hardware.h gpu: host1x: Support 40-bit addressing 2019-02-07 18:28:35 +01:00
host1x07.c gpu: host1x: Add Tegra194 support 2018-11-29 17:11:49 +01:00
host1x07.h gpu: host1x: Add Tegra194 support 2018-11-29 17:11:49 +01:00
hw_host1x01_channel.h
hw_host1x01_sync.h gpu: host1x: Fix MLOCK's debug info 2015-10-02 14:40:12 +02:00
hw_host1x01_uclass.h
hw_host1x02_channel.h
hw_host1x02_sync.h gpu: host1x: Fix MLOCK's debug info 2015-10-02 14:40:12 +02:00
hw_host1x02_uclass.h
hw_host1x04_channel.h gpu: host1x: Enable gather filter 2017-10-20 14:19:52 +02:00
hw_host1x04_sync.h gpu: host1x: Fix MLOCK's debug info 2015-10-02 14:40:12 +02:00
hw_host1x04_uclass.h
hw_host1x05_channel.h gpu: host1x: Enable gather filter 2017-10-20 14:19:52 +02:00
hw_host1x05_sync.h gpu: host1x: Add Tegra210 support 2015-12-14 10:50:33 +01:00
hw_host1x05_uclass.h gpu: host1x: Add Tegra210 support 2015-12-14 10:50:33 +01:00
hw_host1x06_channel.h gpu: host1x: Program the channel stream ID 2019-02-07 18:28:33 +01:00
hw_host1x06_hypervisor.h gpu: host1x: Add Tegra186 support 2017-10-20 14:19:51 +02:00
hw_host1x06_uclass.h gpu: host1x: Fix syncpoint ID field size on Tegra186 2018-11-27 17:18:39 +01:00
hw_host1x06_vm.h gpu: host1x: Add Tegra186 support 2017-10-20 14:19:51 +02:00
hw_host1x07_channel.h gpu: host1x: Program the channel stream ID 2019-02-07 18:28:33 +01:00
hw_host1x07_hypervisor.h gpu: host1x: Add Tegra194 support 2018-11-29 17:11:49 +01:00
hw_host1x07_uclass.h gpu: host1x: Add Tegra194 support 2018-11-29 17:11:49 +01:00
hw_host1x07_vm.h gpu: host1x: Add Tegra194 support 2018-11-29 17:11:49 +01:00
intr_hw.c gpu: host1x: Add Tegra186 support 2017-10-20 14:19:51 +02:00
syncpt_hw.c gpu: host1x: Add Tegra194 support 2018-11-29 17:11:49 +01:00