Joseph Gravenor 639dcfc6fe drm/amd/display: have two different sr and pstate latency tables for renoir ... [Why] new sr and pstate latencies are optimized for the case when we are not using lpddr4 memory [How] have two different wm tables, one for the lpddr case and one for non lpddr case Signed-off-by: Joseph Gravenor <joseph.gravenor@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2019-12-05 16:28:50 -05:00
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dce100	drm/amd/display: move dispclk vco freq to clk mgr base	2019-10-25 16:50:08 -04:00
dce110	drm/amdgpu/display: fix 64 bit divide	2019-10-03 09:11:00 -05:00
dce112	drm/amd/display: rename core_dc to dc	2019-12-05 16:26:39 -05:00
dce120	drm/amd/display: Copy max_clks_by_state after dce_clk_mgr_construct	2019-07-18 14:18:09 -05:00
dcn10	drm/amd/display: rename core_dc to dc	2019-12-05 16:26:39 -05:00
dcn20	drm/amd/display: Make clk mgr the only dto update point	2019-10-25 16:50:09 -04:00
dcn21	drm/amd/display: have two different sr and pstate latency tables for renoir	2019-12-05 16:28:50 -05:00
clk_mgr.c	drm/amd/display: Fix Dali clk mgr construct	2019-12-05 16:26:54 -05:00
Makefile	drm/amd/display: rename DCN1_0 kconfig to DCN	2019-11-13 15:29:44 -05:00