forked from Minki/linux
941aefac4c
Allow the generic sleep code to be used with SMP CPU idle by storing N CPU stack pointers rather than just one. Tested on Assabet and Tegra 2. Tested-by: Colin Cross <ccross@android.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
135 lines
3.5 KiB
ArmAsm
135 lines
3.5 KiB
ArmAsm
#include <linux/linkage.h>
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#include <linux/threads.h>
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#include <asm/asm-offsets.h>
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#include <asm/assembler.h>
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#include <asm/glue-cache.h>
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#include <asm/glue-proc.h>
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#include <asm/system.h>
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.text
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/*
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* Save CPU state for a suspend
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* r1 = v:p offset
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* r3 = virtual return function
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* Note: sp is decremented to allocate space for CPU state on stack
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* r0-r3,r9,r10,lr corrupted
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*/
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ENTRY(cpu_suspend)
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mov r9, lr
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#ifdef MULTI_CPU
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ldr r10, =processor
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mov r2, sp @ current virtual SP
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ldr r0, [r10, #CPU_SLEEP_SIZE] @ size of CPU sleep state
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ldr ip, [r10, #CPU_DO_RESUME] @ virtual resume function
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sub sp, sp, r0 @ allocate CPU state on stack
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mov r0, sp @ save pointer
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add ip, ip, r1 @ convert resume fn to phys
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stmfd sp!, {r1, r2, r3, ip} @ save v:p, virt SP, retfn, phys resume fn
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ldr r3, =sleep_save_sp
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add r2, sp, r1 @ convert SP to phys
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#ifdef CONFIG_SMP
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ALT_SMP(mrc p15, 0, lr, c0, c0, 5)
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ALT_UP(mov lr, #0)
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and lr, lr, #15
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str r2, [r3, lr, lsl #2] @ save phys SP
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#else
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str r2, [r3] @ save phys SP
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#endif
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mov lr, pc
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ldr pc, [r10, #CPU_DO_SUSPEND] @ save CPU state
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#else
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mov r2, sp @ current virtual SP
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ldr r0, =cpu_suspend_size
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sub sp, sp, r0 @ allocate CPU state on stack
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mov r0, sp @ save pointer
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stmfd sp!, {r1, r2, r3} @ save v:p, virt SP, return fn
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ldr r3, =sleep_save_sp
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add r2, sp, r1 @ convert SP to phys
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#ifdef CONFIG_SMP
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ALT_SMP(mrc p15, 0, lr, c0, c0, 5)
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ALT_UP(mov lr, #0)
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and lr, lr, #15
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str r2, [r3, lr, lsl #2] @ save phys SP
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#else
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str r2, [r3] @ save phys SP
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#endif
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bl cpu_do_suspend
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#endif
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@ flush data cache
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#ifdef MULTI_CACHE
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ldr r10, =cpu_cache
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mov lr, r9
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ldr pc, [r10, #CACHE_FLUSH_KERN_ALL]
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#else
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mov lr, r9
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b __cpuc_flush_kern_all
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#endif
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ENDPROC(cpu_suspend)
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.ltorg
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/*
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* r0 = control register value
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* r1 = v:p offset (preserved by cpu_do_resume)
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* r2 = phys page table base
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* r3 = L1 section flags
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*/
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ENTRY(cpu_resume_mmu)
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adr r4, cpu_resume_turn_mmu_on
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mov r4, r4, lsr #20
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orr r3, r3, r4, lsl #20
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ldr r5, [r2, r4, lsl #2] @ save old mapping
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str r3, [r2, r4, lsl #2] @ setup 1:1 mapping for mmu code
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sub r2, r2, r1
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ldr r3, =cpu_resume_after_mmu
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bic r1, r0, #CR_C @ ensure D-cache is disabled
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b cpu_resume_turn_mmu_on
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ENDPROC(cpu_resume_mmu)
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.ltorg
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.align 5
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cpu_resume_turn_mmu_on:
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mcr p15, 0, r1, c1, c0, 0 @ turn on MMU, I-cache, etc
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mrc p15, 0, r1, c0, c0, 0 @ read id reg
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mov r1, r1
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mov r1, r1
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mov pc, r3 @ jump to virtual address
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ENDPROC(cpu_resume_turn_mmu_on)
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cpu_resume_after_mmu:
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str r5, [r2, r4, lsl #2] @ restore old mapping
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mcr p15, 0, r0, c1, c0, 0 @ turn on D-cache
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mov pc, lr
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ENDPROC(cpu_resume_after_mmu)
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/*
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* Note: Yes, part of the following code is located into the .data section.
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* This is to allow sleep_save_sp to be accessed with a relative load
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* while we can't rely on any MMU translation. We could have put
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* sleep_save_sp in the .text section as well, but some setups might
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* insist on it to be truly read-only.
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*/
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.data
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.align
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ENTRY(cpu_resume)
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#ifdef CONFIG_SMP
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adr r0, sleep_save_sp
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ALT_SMP(mrc p15, 0, r1, c0, c0, 5)
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ALT_UP(mov r1, #0)
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and r1, r1, #15
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ldr r0, [r0, r1, lsl #2] @ stack phys addr
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#else
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ldr r0, sleep_save_sp @ stack phys addr
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#endif
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msr cpsr_c, #PSR_I_BIT | PSR_F_BIT | SVC_MODE @ set SVC, irqs off
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#ifdef MULTI_CPU
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ldmia r0!, {r1, sp, lr, pc} @ load v:p, stack, return fn, resume fn
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#else
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ldmia r0!, {r1, sp, lr} @ load v:p, stack, return fn
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b cpu_do_resume
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#endif
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ENDPROC(cpu_resume)
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sleep_save_sp:
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.rept CONFIG_NR_CPUS
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.long 0 @ preserve stack phys ptr here
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.endr
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