0e9b114132
This commit adds support for the Broadcom STB S2/S3/S5 suspend states on MIPS based SoCs. This requires quite a lot of code in order to deal with the different HW blocks that need to be quiesced during suspend: - DDR PHY - DDR memory controller and arbiter - control processor The final steps of the suspend execute in cache and there is is a little bit of assembly code in order to shut down the DDR PHY PLL and then go into a wait loop until a wake-up even occurs. Conversely the resume part involves waiting for the DDR PHY PLL to come back up and resume executions where we left. Signed-off-by: Justin Chen <justinpopo6@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
4 lines
137 B
Makefile
4 lines
137 B
Makefile
obj-$(CONFIG_ARM) += s2-arm.o pm-arm.o
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AFLAGS_s2-arm.o := -march=armv7-a
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obj-$(CONFIG_BMIPS_GENERIC) += s2-mips.o s3-mips.o pm-mips.o
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