3032f0c900
- ARCv2 LLSC spinlocks have smp_mb() both before and after the LLSC instructions, which is not required per lkmm ACQ/REL semantics. smp_mb() is only needed _after_ lock and _before_ unlock. So remove the extra barriers. The reason they were there was mainly historical. At the time of initial SMP Linux bringup on HS38 cores, I was too conservative, given the fluidity of both hw and sw. The last attempt to ditch the extra barrier showed some hackbench regression which is apparently not the case now (atleast for LLSC case, read on...) - EX based spinlocks (!CONFIG_ARC_HAS_LLSC) still needs the extra smp_mb(), not due to lkmm, but due to some hardware shenanigans. W/o that, hackbench triggers RCU stall splat so extra DMB is retained !LLSC based systems are not realistic Linux sstem anyways so they can afford to be a nit suboptimal ;-) | [ARCLinux]# for i in (seq 1 1 5) ; do hackbench; done | Running with 10 groups 400 process | INFO: task hackbench:158 blocked for more than 10 seconds. | Not tainted 4.20.0-00005-g96b18288a88e-dirty #117 | "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. | hackbench D 0 158 135 0x00000000 | | Stack Trace: | watchdog: BUG: soft lockup - CPU#3 stuck for 59s! [hackbench:469] | Modules linked in: | Path: (null) | CPU: 3 PID: 469 Comm: hackbench Not tainted 4.20.0-00005-g96b18288a88e-dirty | | [ECR ]: 0x00000000 => Check Programmer's Manual | [EFA ]: 0x00000000 | [BLINK ]: do_exit+0x4a6/0x7d0 | [ERET ]: _raw_write_unlock_irq+0x44/0x5c - And while at it, remove the extar smp_mb() from EX based arch_read_trylock() since the spin lock there guarantees a full barrier anyways - For LLSC case, hackbench threads improves with this patch (HAPS @ 50MHz) ---- before ---- | | [ARCLinux]# for i in 1 2 3 4 5; do hackbench 10 thread; done | Running with 10 groups 400 threads | Time: 16.253 | Time: 16.445 | Time: 16.590 | Time: 16.721 | Time: 16.544 ---- after ---- | | [ARCLinux]# for i in 1 2 3 4 5; do hackbench 10 thread; done | Running with 10 groups 400 threads | Time: 15.638 | Time: 15.730 | Time: 15.870 | Time: 15.842 | Time: 15.729 Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
392 lines
8.6 KiB
C
392 lines
8.6 KiB
C
/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_SPINLOCK_H
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#define __ASM_SPINLOCK_H
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#include <asm/spinlock_types.h>
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#include <asm/processor.h>
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#include <asm/barrier.h>
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#define arch_spin_is_locked(x) ((x)->slock != __ARCH_SPIN_LOCK_UNLOCKED__)
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#ifdef CONFIG_ARC_HAS_LLSC
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static inline void arch_spin_lock(arch_spinlock_t *lock)
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{
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unsigned int val;
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__asm__ __volatile__(
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"1: llock %[val], [%[slock]] \n"
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" breq %[val], %[LOCKED], 1b \n" /* spin while LOCKED */
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" scond %[LOCKED], [%[slock]] \n" /* acquire */
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" bnz 1b \n"
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" \n"
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: [val] "=&r" (val)
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: [slock] "r" (&(lock->slock)),
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[LOCKED] "r" (__ARCH_SPIN_LOCK_LOCKED__)
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: "memory", "cc");
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/*
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* ACQUIRE barrier to ensure load/store after taking the lock
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* don't "bleed-up" out of the critical section (leak-in is allowed)
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* http://www.spinics.net/lists/kernel/msg2010409.html
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*
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* ARCv2 only has load-load, store-store and all-all barrier
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* thus need the full all-all barrier
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*/
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smp_mb();
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}
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/* 1 - lock taken successfully */
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static inline int arch_spin_trylock(arch_spinlock_t *lock)
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{
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unsigned int val, got_it = 0;
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__asm__ __volatile__(
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"1: llock %[val], [%[slock]] \n"
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" breq %[val], %[LOCKED], 4f \n" /* already LOCKED, just bail */
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" scond %[LOCKED], [%[slock]] \n" /* acquire */
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" bnz 1b \n"
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" mov %[got_it], 1 \n"
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"4: \n"
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" \n"
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: [val] "=&r" (val),
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[got_it] "+&r" (got_it)
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: [slock] "r" (&(lock->slock)),
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[LOCKED] "r" (__ARCH_SPIN_LOCK_LOCKED__)
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: "memory", "cc");
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smp_mb();
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return got_it;
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}
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static inline void arch_spin_unlock(arch_spinlock_t *lock)
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{
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smp_mb();
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WRITE_ONCE(lock->slock, __ARCH_SPIN_LOCK_UNLOCKED__);
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}
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/*
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* Read-write spinlocks, allowing multiple readers but only one writer.
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* Unfair locking as Writers could be starved indefinitely by Reader(s)
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*/
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static inline void arch_read_lock(arch_rwlock_t *rw)
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{
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unsigned int val;
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/*
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* zero means writer holds the lock exclusively, deny Reader.
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* Otherwise grant lock to first/subseq reader
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*
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* if (rw->counter > 0) {
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* rw->counter--;
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* ret = 1;
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* }
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*/
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__asm__ __volatile__(
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"1: llock %[val], [%[rwlock]] \n"
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" brls %[val], %[WR_LOCKED], 1b\n" /* <= 0: spin while write locked */
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" sub %[val], %[val], 1 \n" /* reader lock */
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" scond %[val], [%[rwlock]] \n"
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" bnz 1b \n"
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" \n"
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: [val] "=&r" (val)
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: [rwlock] "r" (&(rw->counter)),
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[WR_LOCKED] "ir" (0)
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: "memory", "cc");
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smp_mb();
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}
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/* 1 - lock taken successfully */
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static inline int arch_read_trylock(arch_rwlock_t *rw)
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{
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unsigned int val, got_it = 0;
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__asm__ __volatile__(
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"1: llock %[val], [%[rwlock]] \n"
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" brls %[val], %[WR_LOCKED], 4f\n" /* <= 0: already write locked, bail */
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" sub %[val], %[val], 1 \n" /* counter-- */
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" scond %[val], [%[rwlock]] \n"
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" bnz 1b \n" /* retry if collided with someone */
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" mov %[got_it], 1 \n"
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" \n"
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"4: ; --- done --- \n"
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: [val] "=&r" (val),
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[got_it] "+&r" (got_it)
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: [rwlock] "r" (&(rw->counter)),
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[WR_LOCKED] "ir" (0)
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: "memory", "cc");
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smp_mb();
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return got_it;
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}
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static inline void arch_write_lock(arch_rwlock_t *rw)
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{
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unsigned int val;
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/*
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* If reader(s) hold lock (lock < __ARCH_RW_LOCK_UNLOCKED__),
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* deny writer. Otherwise if unlocked grant to writer
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* Hence the claim that Linux rwlocks are unfair to writers.
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* (can be starved for an indefinite time by readers).
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*
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* if (rw->counter == __ARCH_RW_LOCK_UNLOCKED__) {
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* rw->counter = 0;
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* ret = 1;
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* }
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*/
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__asm__ __volatile__(
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"1: llock %[val], [%[rwlock]] \n"
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" brne %[val], %[UNLOCKED], 1b \n" /* while !UNLOCKED spin */
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" mov %[val], %[WR_LOCKED] \n"
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" scond %[val], [%[rwlock]] \n"
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" bnz 1b \n"
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" \n"
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: [val] "=&r" (val)
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: [rwlock] "r" (&(rw->counter)),
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[UNLOCKED] "ir" (__ARCH_RW_LOCK_UNLOCKED__),
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[WR_LOCKED] "ir" (0)
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: "memory", "cc");
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smp_mb();
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}
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/* 1 - lock taken successfully */
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static inline int arch_write_trylock(arch_rwlock_t *rw)
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{
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unsigned int val, got_it = 0;
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__asm__ __volatile__(
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"1: llock %[val], [%[rwlock]] \n"
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" brne %[val], %[UNLOCKED], 4f \n" /* !UNLOCKED, bail */
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" mov %[val], %[WR_LOCKED] \n"
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" scond %[val], [%[rwlock]] \n"
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" bnz 1b \n" /* retry if collided with someone */
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" mov %[got_it], 1 \n"
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" \n"
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"4: ; --- done --- \n"
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: [val] "=&r" (val),
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[got_it] "+&r" (got_it)
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: [rwlock] "r" (&(rw->counter)),
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[UNLOCKED] "ir" (__ARCH_RW_LOCK_UNLOCKED__),
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[WR_LOCKED] "ir" (0)
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: "memory", "cc");
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smp_mb();
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return got_it;
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}
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static inline void arch_read_unlock(arch_rwlock_t *rw)
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{
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unsigned int val;
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smp_mb();
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/*
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* rw->counter++;
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*/
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__asm__ __volatile__(
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"1: llock %[val], [%[rwlock]] \n"
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" add %[val], %[val], 1 \n"
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" scond %[val], [%[rwlock]] \n"
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" bnz 1b \n"
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" \n"
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: [val] "=&r" (val)
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: [rwlock] "r" (&(rw->counter))
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: "memory", "cc");
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}
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static inline void arch_write_unlock(arch_rwlock_t *rw)
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{
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smp_mb();
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WRITE_ONCE(rw->counter, __ARCH_RW_LOCK_UNLOCKED__);
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}
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#else /* !CONFIG_ARC_HAS_LLSC */
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static inline void arch_spin_lock(arch_spinlock_t *lock)
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{
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unsigned int val = __ARCH_SPIN_LOCK_LOCKED__;
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/*
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* Per lkmm, smp_mb() is only required after _lock (and before_unlock)
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* for ACQ and REL semantics respectively. However EX based spinlocks
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* need the extra smp_mb to workaround a hardware quirk.
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*/
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smp_mb();
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__asm__ __volatile__(
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"1: ex %0, [%1] \n"
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#ifdef CONFIG_EZNPS_MTM_EXT
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" .word %3 \n"
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#endif
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" breq %0, %2, 1b \n"
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: "+&r" (val)
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: "r"(&(lock->slock)), "ir"(__ARCH_SPIN_LOCK_LOCKED__)
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#ifdef CONFIG_EZNPS_MTM_EXT
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, "i"(CTOP_INST_SCHD_RW)
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#endif
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: "memory");
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smp_mb();
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}
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/* 1 - lock taken successfully */
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static inline int arch_spin_trylock(arch_spinlock_t *lock)
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{
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unsigned int val = __ARCH_SPIN_LOCK_LOCKED__;
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smp_mb();
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__asm__ __volatile__(
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"1: ex %0, [%1] \n"
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: "+r" (val)
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: "r"(&(lock->slock))
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: "memory");
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smp_mb();
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return (val == __ARCH_SPIN_LOCK_UNLOCKED__);
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}
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static inline void arch_spin_unlock(arch_spinlock_t *lock)
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{
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unsigned int val = __ARCH_SPIN_LOCK_UNLOCKED__;
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/*
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* RELEASE barrier: given the instructions avail on ARCv2, full barrier
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* is the only option
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*/
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smp_mb();
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/*
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* EX is not really required here, a simple STore of 0 suffices.
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* However this causes tasklist livelocks in SystemC based SMP virtual
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* platforms where the systemc core scheduler uses EX as a cue for
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* moving to next core. Do a git log of this file for details
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*/
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__asm__ __volatile__(
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" ex %0, [%1] \n"
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: "+r" (val)
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: "r"(&(lock->slock))
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: "memory");
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/*
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* see pairing version/comment in arch_spin_lock above
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*/
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smp_mb();
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}
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/*
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* Read-write spinlocks, allowing multiple readers but only one writer.
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* Unfair locking as Writers could be starved indefinitely by Reader(s)
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*
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* The spinlock itself is contained in @counter and access to it is
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* serialized with @lock_mutex.
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*/
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/* 1 - lock taken successfully */
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static inline int arch_read_trylock(arch_rwlock_t *rw)
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{
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int ret = 0;
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unsigned long flags;
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local_irq_save(flags);
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arch_spin_lock(&(rw->lock_mutex));
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/*
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* zero means writer holds the lock exclusively, deny Reader.
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* Otherwise grant lock to first/subseq reader
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*/
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if (rw->counter > 0) {
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rw->counter--;
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ret = 1;
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}
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arch_spin_unlock(&(rw->lock_mutex));
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local_irq_restore(flags);
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return ret;
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}
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/* 1 - lock taken successfully */
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static inline int arch_write_trylock(arch_rwlock_t *rw)
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{
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int ret = 0;
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unsigned long flags;
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local_irq_save(flags);
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arch_spin_lock(&(rw->lock_mutex));
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/*
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* If reader(s) hold lock (lock < __ARCH_RW_LOCK_UNLOCKED__),
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* deny writer. Otherwise if unlocked grant to writer
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* Hence the claim that Linux rwlocks are unfair to writers.
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* (can be starved for an indefinite time by readers).
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*/
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if (rw->counter == __ARCH_RW_LOCK_UNLOCKED__) {
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rw->counter = 0;
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ret = 1;
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}
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arch_spin_unlock(&(rw->lock_mutex));
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local_irq_restore(flags);
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return ret;
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}
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static inline void arch_read_lock(arch_rwlock_t *rw)
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{
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while (!arch_read_trylock(rw))
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cpu_relax();
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}
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static inline void arch_write_lock(arch_rwlock_t *rw)
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{
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while (!arch_write_trylock(rw))
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cpu_relax();
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}
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static inline void arch_read_unlock(arch_rwlock_t *rw)
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{
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unsigned long flags;
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local_irq_save(flags);
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arch_spin_lock(&(rw->lock_mutex));
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rw->counter++;
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arch_spin_unlock(&(rw->lock_mutex));
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local_irq_restore(flags);
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}
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static inline void arch_write_unlock(arch_rwlock_t *rw)
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{
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unsigned long flags;
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local_irq_save(flags);
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arch_spin_lock(&(rw->lock_mutex));
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rw->counter = __ARCH_RW_LOCK_UNLOCKED__;
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arch_spin_unlock(&(rw->lock_mutex));
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local_irq_restore(flags);
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}
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#endif
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#endif /* __ASM_SPINLOCK_H */
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