linux/arch/openrisc
Stafford Horne 610f01b9a8 openrisc: fix possible deadlock scenario during timer sync
OpenRISC borrows its timer sync logic from MIPS, Matt helped to review
the OpenRISC implementation and noted that we may suffer the same
deadlock case that MIPS has faced. The case being:

  "the MIPS timer synchronization code contained the possibility of
  deadlock. If you mark a CPU online before it goes into the synchronize
  loop, then the boot CPU can schedule a different thread and send IPIs to
  all "online" CPUs. It gets stuck waiting for the secondary to ack it's
  IPI, since this secondary CPU has not enabled IRQs yet, and is stuck
  waiting for the master to synchronise with it.  The system then
  deadlocks."

Fix this by moving set_cpu_online() to after timer sync.

Reported-by: Matt Redfearn <matt.redfearn@mips.com>
Signed-off-by: Stafford Horne <shorne@gmail.com>
2017-11-03 14:01:17 +09:00
..
boot/dts openrisc: add simple_smp dts and defconfig for simulators 2017-11-03 14:01:15 +09:00
configs openrisc: add simple_smp dts and defconfig for simulators 2017-11-03 14:01:15 +09:00
include openrisc: add tick timer multi-core sync logic 2017-11-03 14:01:16 +09:00
kernel openrisc: fix possible deadlock scenario during timer sync 2017-11-03 14:01:17 +09:00
lib openrisc: initial SMP support 2017-11-03 14:01:13 +09:00
mm openrisc: add cacheflush support to fix icache aliasing 2017-11-03 14:01:15 +09:00
Kconfig openrisc: enable LOCKDEP_SUPPORT and irqflags tracing 2017-11-03 14:01:16 +09:00
Makefile openrisc: pass endianness info to sparse 2017-11-03 14:01:17 +09:00