5e93cbadd3
When a data path reset is initiated, write control to the PCIE_GMBX is yanked from the switch manager. The switch manager writes to this register to clear mailbox global interrupt bits as part of its mailbox interrupt handling routine. When the device recovers from the data path reset and these bits are not cleared, it will prevent future mailbox global interrupts from being triggered. Upon confirming that the device has exited from a data path reset, clear these bits to ensure the proper functioning of the mailbox global interrupt. Signed-off-by: Ngai-Mint Kwan <ngai-mint.kwan@intel.com> Signed-off-by: Jacob Keller <jacob.e.keller@intel.com> Tested-by: Krishneil Singh <Krishneil.k.singh@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> |
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| .. | ||
| e1000 | ||
| e1000e | ||
| fm10k | ||
| i40e | ||
| i40evf | ||
| igb | ||
| igbvf | ||
| ixgb | ||
| ixgbe | ||
| ixgbevf | ||
| e100.c | ||
| Kconfig | ||
| Makefile | ||