forked from Minki/linux
a4e2e2ac08
If we make all QSPI (SPI protocol) addressing consistent across all ColdFire family members then we will be able to remove the duplicated plaform data and code and use a single setup for all. So modify the ColdFire 520x QSPI addressing so that: . base addresses are absolute (not relative to MBAR peripheral register) . use a common name for IRQs used . move chip select definitions (CS) to appropriate header Signed-off-by: Greg Ungerer <gerg@uclinux.org>
191 lines
6.5 KiB
C
191 lines
6.5 KiB
C
/****************************************************************************/
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/*
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* m520xsim.h -- ColdFire 5207/5208 System Integration Module support.
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*
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* (C) Copyright 2005, Intec Automation (mike@steroidmicros.com)
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*/
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/****************************************************************************/
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#ifndef m520xsim_h
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#define m520xsim_h
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/****************************************************************************/
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#define CPU_NAME "COLDFIRE(m520x)"
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#define CPU_INSTR_PER_JIFFY 3
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#define MCF_BUSCLK (MCF_CLK / 2)
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#include <asm/m52xxacr.h>
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/*
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* Define the 520x SIM register set addresses.
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*/
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#define MCFICM_INTC0 0xFC048000 /* Base for Interrupt Ctrl 0 */
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#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
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#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
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#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
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#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
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#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
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#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
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#define MCFINTC_SIMR 0x1c /* Set interrupt mask 0-63 */
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#define MCFINTC_CIMR 0x1d /* Clear interrupt mask 0-63 */
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#define MCFINTC_ICR0 0x40 /* Base ICR register */
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/*
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* The common interrupt controller code just wants to know the absolute
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* address to the SIMR and CIMR registers (not offsets into IPSBAR).
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* The 520x family only has a single INTC unit.
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*/
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#define MCFINTC0_SIMR (MCFICM_INTC0 + MCFINTC_SIMR)
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#define MCFINTC0_CIMR (MCFICM_INTC0 + MCFINTC_CIMR)
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#define MCFINTC0_ICR0 (MCFICM_INTC0 + MCFINTC_ICR0)
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#define MCFINTC1_SIMR (0)
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#define MCFINTC1_CIMR (0)
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#define MCFINTC1_ICR0 (0)
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#define MCFINT_VECBASE 64
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#define MCFINT_UART0 26 /* Interrupt number for UART0 */
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#define MCFINT_UART1 27 /* Interrupt number for UART1 */
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#define MCFINT_UART2 28 /* Interrupt number for UART2 */
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#define MCFINT_QSPI 31 /* Interrupt number for QSPI */
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#define MCFINT_FECRX0 36 /* Interrupt number for FEC RX */
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#define MCFINT_FECTX0 40 /* Interrupt number for FEC RX */
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#define MCFINT_FECENTC0 42 /* Interrupt number for FEC RX */
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#define MCFINT_PIT1 4 /* Interrupt number for PIT1 (PIT0 in processor) */
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#define MCF_IRQ_UART0 (MCFINT_VECBASE + MCFINT_UART0)
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#define MCF_IRQ_UART1 (MCFINT_VECBASE + MCFINT_UART1)
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#define MCF_IRQ_UART2 (MCFINT_VECBASE + MCFINT_UART2)
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#define MCF_IRQ_FECRX0 (MCFINT_VECBASE + MCFINT_FECRX0)
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#define MCF_IRQ_FECTX0 (MCFINT_VECBASE + MCFINT_FECTX0)
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#define MCF_IRQ_FECENTC0 (MCFINT_VECBASE + MCFINT_FECENTC0)
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#define MCF_IRQ_QSPI (MCFINT_VECBASE + MCFINT_QSPI)
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/*
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* SDRAM configuration registers.
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*/
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#define MCFSIM_SDMR 0xFC0a8000 /* SDRAM Mode/Extended Mode Register */
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#define MCFSIM_SDCR 0xFC0a8004 /* SDRAM Control Register */
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#define MCFSIM_SDCFG1 0xFC0a8008 /* SDRAM Configuration Register 1 */
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#define MCFSIM_SDCFG2 0xFC0a800c /* SDRAM Configuration Register 2 */
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#define MCFSIM_SDCS0 0xFC0a8110 /* SDRAM Chip Select 0 Configuration */
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#define MCFSIM_SDCS1 0xFC0a8114 /* SDRAM Chip Select 1 Configuration */
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/*
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* EPORT and GPIO registers.
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*/
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#define MCFEPORT_EPPAR 0xFC088000
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#define MCFEPORT_EPDDR 0xFC088002
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#define MCFEPORT_EPIER 0xFC088003
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#define MCFEPORT_EPDR 0xFC088004
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#define MCFEPORT_EPPDR 0xFC088005
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#define MCFEPORT_EPFR 0xFC088006
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#define MCFGPIO_PODR_BUSCTL 0xFC0A4000
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#define MCFGPIO_PODR_BE 0xFC0A4001
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#define MCFGPIO_PODR_CS 0xFC0A4002
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#define MCFGPIO_PODR_FECI2C 0xFC0A4003
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#define MCFGPIO_PODR_QSPI 0xFC0A4004
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#define MCFGPIO_PODR_TIMER 0xFC0A4005
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#define MCFGPIO_PODR_UART 0xFC0A4006
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#define MCFGPIO_PODR_FECH 0xFC0A4007
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#define MCFGPIO_PODR_FECL 0xFC0A4008
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#define MCFGPIO_PDDR_BUSCTL 0xFC0A400C
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#define MCFGPIO_PDDR_BE 0xFC0A400D
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#define MCFGPIO_PDDR_CS 0xFC0A400E
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#define MCFGPIO_PDDR_FECI2C 0xFC0A400F
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#define MCFGPIO_PDDR_QSPI 0xFC0A4010
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#define MCFGPIO_PDDR_TIMER 0xFC0A4011
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#define MCFGPIO_PDDR_UART 0xFC0A4012
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#define MCFGPIO_PDDR_FECH 0xFC0A4013
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#define MCFGPIO_PDDR_FECL 0xFC0A4014
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#define MCFGPIO_PPDSDR_CS 0xFC0A401A
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#define MCFGPIO_PPDSDR_FECI2C 0xFC0A401B
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#define MCFGPIO_PPDSDR_QSPI 0xFC0A401C
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#define MCFGPIO_PPDSDR_TIMER 0xFC0A401D
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#define MCFGPIO_PPDSDR_UART 0xFC0A401E
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#define MCFGPIO_PPDSDR_FECH 0xFC0A401F
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#define MCFGPIO_PPDSDR_FECL 0xFC0A4020
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#define MCFGPIO_PCLRR_BUSCTL 0xFC0A4024
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#define MCFGPIO_PCLRR_BE 0xFC0A4025
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#define MCFGPIO_PCLRR_CS 0xFC0A4026
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#define MCFGPIO_PCLRR_FECI2C 0xFC0A4027
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#define MCFGPIO_PCLRR_QSPI 0xFC0A4028
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#define MCFGPIO_PCLRR_TIMER 0xFC0A4029
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#define MCFGPIO_PCLRR_UART 0xFC0A402A
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#define MCFGPIO_PCLRR_FECH 0xFC0A402B
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#define MCFGPIO_PCLRR_FECL 0xFC0A402C
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/*
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* Generic GPIO support
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*/
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#define MCFGPIO_PODR MCFGPIO_PODR_CS
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#define MCFGPIO_PDDR MCFGPIO_PDDR_CS
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#define MCFGPIO_PPDR MCFGPIO_PPDSDR_CS
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#define MCFGPIO_SETR MCFGPIO_PPDSDR_CS
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#define MCFGPIO_CLRR MCFGPIO_PCLRR_CS
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#define MCFGPIO_PIN_MAX 80
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#define MCFGPIO_IRQ_MAX 8
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#define MCFGPIO_IRQ_VECBASE MCFINT_VECBASE
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#define MCF_GPIO_PAR_UART 0xFC0A4036
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#define MCF_GPIO_PAR_FECI2C 0xFC0A4033
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#define MCF_GPIO_PAR_QSPI 0xFC0A4034
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#define MCF_GPIO_PAR_FEC 0xFC0A4038
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#define MCF_GPIO_PAR_UART_PAR_URXD0 (0x0001)
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#define MCF_GPIO_PAR_UART_PAR_UTXD0 (0x0002)
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#define MCF_GPIO_PAR_UART_PAR_URXD1 (0x0040)
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#define MCF_GPIO_PAR_UART_PAR_UTXD1 (0x0080)
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#define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2 (0x02)
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#define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2 (0x04)
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/*
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* PIT timer module.
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*/
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#define MCFPIT_BASE1 0xFC080000 /* Base address of TIMER1 */
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#define MCFPIT_BASE2 0xFC084000 /* Base address of TIMER2 */
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/*
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* UART module.
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*/
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#define MCFUART_BASE0 0xFC060000 /* Base address of UART0 */
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#define MCFUART_BASE1 0xFC064000 /* Base address of UART1 */
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#define MCFUART_BASE2 0xFC068000 /* Base address of UART2 */
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/*
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* FEC module.
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*/
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#define MCFFEC_BASE0 0xFC030000 /* Base of FEC ethernet */
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#define MCFFEC_SIZE0 0x800 /* Register set size */
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/*
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* QSPI module.
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*/
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#define MCFQSPI_BASE 0xFC05C000 /* Base of QSPI module */
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#define MCFQSPI_SIZE 0x40 /* Register set size */
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#define MCFQSPI_CS0 46
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#define MCFQSPI_CS1 47
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#define MCFQSPI_CS2 27
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/*
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* Reset Control Unit.
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*/
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#define MCF_RCR 0xFC0A0000
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#define MCF_RSR 0xFC0A0001
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#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
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#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
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/****************************************************************************/
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#endif /* m520xsim_h */
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