53bf7f7a43
The arguments related to IOMMU port name have been unused since
commit 944fc36c31 ("drm/msm: use upstream iommu") and can be removed.
Signed-off-by: Drew Davenport <ddavenport@chromium.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
124 lines
3.0 KiB
C
124 lines
3.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Copyright (c) 2018 The Linux Foundation. All rights reserved. */
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#include <linux/dma-mapping.h>
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#include "msm_drv.h"
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#include "msm_mmu.h"
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#include "adreno/adreno_gpu.h"
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#include "adreno/a2xx.xml.h"
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struct msm_gpummu {
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struct msm_mmu base;
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struct msm_gpu *gpu;
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dma_addr_t pt_base;
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uint32_t *table;
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};
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#define to_msm_gpummu(x) container_of(x, struct msm_gpummu, base)
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#define GPUMMU_VA_START SZ_16M
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#define GPUMMU_VA_RANGE (0xfff * SZ_64K)
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#define GPUMMU_PAGE_SIZE SZ_4K
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#define TABLE_SIZE (sizeof(uint32_t) * GPUMMU_VA_RANGE / GPUMMU_PAGE_SIZE)
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static int msm_gpummu_attach(struct msm_mmu *mmu)
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{
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return 0;
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}
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static void msm_gpummu_detach(struct msm_mmu *mmu)
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{
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}
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static int msm_gpummu_map(struct msm_mmu *mmu, uint64_t iova,
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struct sg_table *sgt, unsigned len, int prot)
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{
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struct msm_gpummu *gpummu = to_msm_gpummu(mmu);
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unsigned idx = (iova - GPUMMU_VA_START) / GPUMMU_PAGE_SIZE;
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struct scatterlist *sg;
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unsigned prot_bits = 0;
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unsigned i, j;
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if (prot & IOMMU_WRITE)
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prot_bits |= 1;
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if (prot & IOMMU_READ)
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prot_bits |= 2;
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for_each_sg(sgt->sgl, sg, sgt->nents, i) {
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dma_addr_t addr = sg->dma_address;
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for (j = 0; j < sg->length / GPUMMU_PAGE_SIZE; j++, idx++) {
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gpummu->table[idx] = addr | prot_bits;
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addr += GPUMMU_PAGE_SIZE;
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}
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}
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/* we can improve by deferring flush for multiple map() */
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gpu_write(gpummu->gpu, REG_A2XX_MH_MMU_INVALIDATE,
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A2XX_MH_MMU_INVALIDATE_INVALIDATE_ALL |
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A2XX_MH_MMU_INVALIDATE_INVALIDATE_TC);
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return 0;
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}
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static int msm_gpummu_unmap(struct msm_mmu *mmu, uint64_t iova, unsigned len)
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{
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struct msm_gpummu *gpummu = to_msm_gpummu(mmu);
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unsigned idx = (iova - GPUMMU_VA_START) / GPUMMU_PAGE_SIZE;
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unsigned i;
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for (i = 0; i < len / GPUMMU_PAGE_SIZE; i++, idx++)
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gpummu->table[idx] = 0;
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gpu_write(gpummu->gpu, REG_A2XX_MH_MMU_INVALIDATE,
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A2XX_MH_MMU_INVALIDATE_INVALIDATE_ALL |
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A2XX_MH_MMU_INVALIDATE_INVALIDATE_TC);
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return 0;
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}
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static void msm_gpummu_destroy(struct msm_mmu *mmu)
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{
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struct msm_gpummu *gpummu = to_msm_gpummu(mmu);
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dma_free_attrs(mmu->dev, TABLE_SIZE, gpummu->table, gpummu->pt_base,
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DMA_ATTR_FORCE_CONTIGUOUS);
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kfree(gpummu);
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}
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static const struct msm_mmu_funcs funcs = {
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.attach = msm_gpummu_attach,
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.detach = msm_gpummu_detach,
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.map = msm_gpummu_map,
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.unmap = msm_gpummu_unmap,
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.destroy = msm_gpummu_destroy,
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};
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struct msm_mmu *msm_gpummu_new(struct device *dev, struct msm_gpu *gpu)
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{
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struct msm_gpummu *gpummu;
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gpummu = kzalloc(sizeof(*gpummu), GFP_KERNEL);
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if (!gpummu)
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return ERR_PTR(-ENOMEM);
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gpummu->table = dma_alloc_attrs(dev, TABLE_SIZE + 32, &gpummu->pt_base,
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GFP_KERNEL | __GFP_ZERO, DMA_ATTR_FORCE_CONTIGUOUS);
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if (!gpummu->table) {
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kfree(gpummu);
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return ERR_PTR(-ENOMEM);
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}
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gpummu->gpu = gpu;
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msm_mmu_init(&gpummu->base, dev, &funcs);
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return &gpummu->base;
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}
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void msm_gpummu_params(struct msm_mmu *mmu, dma_addr_t *pt_base,
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dma_addr_t *tran_error)
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{
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dma_addr_t base = to_msm_gpummu(mmu)->pt_base;
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*pt_base = base;
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*tran_error = base + TABLE_SIZE; /* 32-byte aligned */
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}
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