linux/drivers/clk/renesas
Geert Uytterhoeven e1f1ae8002 clk: renesas: cpg-mssr: Fix reset control race condition
The module reset code in the Renesas CPG/MSSR driver uses
read-modify-write (RMW) operations to write to a Software Reset Register
(SRCRn), and simple writes to write to a Software Reset Clearing
Register (SRSTCLRn), as was mandated by the R-Car Gen2 and Gen3 Hardware
User's Manuals.

However, this may cause a race condition when two devices are reset in
parallel: if the reset for device A completes in the middle of the RMW
operation for device B, device A may be reset again, causing subtle
failures (e.g. i2c timeouts):

	thread A			thread B
	--------			--------

	val = SRCRn
	val |= bit A
	SRCRn = val

	delay

					val = SRCRn (bit A is set)

	SRSTCLRn = bit A
	(bit A in SRCRn is cleared)

					val |= bit B
					SRCRn = val (bit A and B are set)

This can be reproduced on e.g. Salvator-XS using:

    $ while true; do i2cdump -f -y 4 0x6A b > /dev/null; done &
    $ while true; do i2cdump -f -y 2 0x10 b > /dev/null; done &

    i2c-rcar e6510000.i2c: error -110 : 40000002
    i2c-rcar e66d8000.i2c: error -110 : 40000002

According to the R-Car Gen3 Hardware Manual Errata for Rev.
0.80 of Feb 28, 2018, reflected in Rev. 1.00 of the R-Car Gen3 Hardware
User's Manual, writes to SRCRn do not require read-modify-write cycles.

Note that the R-Car Gen2 Hardware User's Manual has not been updated
yet, and still says a read-modify-write sequence is required.  According
to the hardware team, the reset hardware block is the same on both R-Car
Gen2 and Gen3, though.

Hence fix the issue by replacing the read-modify-write operations on
SRCRn by simple writes.

Reported-by: Yao Lihua <Lihua.Yao@desay-svautomotive.com>
Fixes: 6197aa65c4 ("clk: renesas: cpg-mssr: Add support for reset control")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Linh Phung <linh.phung.jy@renesas.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-07-22 15:04:54 -07:00
..
clk-div6.c clk: renesas: div6: Combine clock-private and parent array allocation 2019-06-20 11:36:29 +02:00
clk-div6.h We have two changes to the core framework this time around. The first being a 2017-11-17 20:04:24 -08:00
clk-emev2.c Merge branches 'clk-dt-name', 'clk-ti-of-node' and 'clk-sa' into clk-next 2018-10-18 15:33:52 -07:00
clk-mstp.c clk: renesas: mstp: Combine group-private and clock array allocation 2019-06-20 11:36:44 +02:00
clk-r8a73a4.c clk: Remove io.h from clk-provider.h 2019-05-15 13:21:37 -07:00
clk-r8a7740.c clk: Remove io.h from clk-provider.h 2019-05-15 13:21:37 -07:00
clk-r8a7778.c Merge branches 'clk-dt-name', 'clk-ti-of-node' and 'clk-sa' into clk-next 2018-10-18 15:33:52 -07:00
clk-r8a7779.c Merge branches 'clk-dt-name', 'clk-ti-of-node' and 'clk-sa' into clk-next 2018-10-18 15:33:52 -07:00
clk-rcar-gen2.c clk: Remove io.h from clk-provider.h 2019-05-15 13:21:37 -07:00
clk-rz.c clk: Remove io.h from clk-provider.h 2019-05-15 13:21:37 -07:00
clk-sh73a0.c clk: Remove io.h from clk-provider.h 2019-05-15 13:21:37 -07:00
Kconfig Merge branch 'clk-renesas' into clk-next 2018-10-18 15:38:51 -07:00
Makefile clk: renesas: cpg-mssr: Add r8a774c0 support 2018-09-19 16:42:14 +02:00
r7s9210-cpg-mssr.c clk: renesas: r7s9210: Always use readl() 2019-04-02 09:50:48 +02:00
r8a774a1-cpg-mssr.c clk: renesas: r8a774a1: Add TMU clock 2019-06-18 11:02:51 +02:00
r8a774c0-cpg-mssr.c clk: renesas: rcar-gen3: Correct parent clock of Audio-DMAC 2019-04-02 10:08:35 +02:00
r8a7743-cpg-mssr.c Merge branch 'clk-renesas' into clk-next 2018-10-18 15:38:51 -07:00
r8a7745-cpg-mssr.c clk: renesas: Convert to SPDX identifiers 2018-09-28 17:16:37 -07:00
r8a7790-cpg-mssr.c clk: renesas: Convert to SPDX identifiers 2018-09-28 17:16:37 -07:00
r8a7791-cpg-mssr.c clk: renesas: Convert to SPDX identifiers 2018-09-28 17:16:37 -07:00
r8a7792-cpg-mssr.c clk: renesas: Convert to SPDX identifiers 2018-09-28 17:16:37 -07:00
r8a7794-cpg-mssr.c clk: renesas: Convert to SPDX identifiers 2018-09-28 17:16:37 -07:00
r8a7795-cpg-mssr.c clk: renesas: r8a7795: Add CMM clocks 2019-06-18 11:02:51 +02:00
r8a7796-cpg-mssr.c clk: renesas: r8a7796: Add CMM clocks 2019-05-21 10:45:09 +02:00
r8a77470-cpg-mssr.c scripts/spelling.txt: add spelling fix for prohibited 2019-07-12 11:05:41 -07:00
r8a77965-cpg-mssr.c clk: renesas: r8a77965: Add CMM clocks 2019-06-18 11:02:54 +02:00
r8a77970-cpg-mssr.c clk: renesas: r8a77970: Add CPEX clock 2018-12-04 10:29:48 +01:00
r8a77980-cpg-mssr.c clk: renesas: r8a77980: Fix RPC-IF module clock's parent 2019-04-02 10:31:05 +02:00
r8a77990-cpg-mssr.c clk: renesas: r8a77990: Add CMM clocks 2019-06-18 11:02:56 +02:00
r8a77995-cpg-mssr.c clk: renesas: r8a77995: Add CMM clocks 2019-06-18 11:03:03 +02:00
r9a06g032-clocks.c clk: renesas: r9a06g032: Add clock domain support 2019-06-04 11:51:00 +02:00
rcar-gen2-cpg.c clk: renesas: Convert to SPDX identifiers 2018-09-28 17:16:37 -07:00
rcar-gen2-cpg.h clk: renesas: Use the correct style for SPDX License Identifier 2019-05-01 13:01:18 -07:00
rcar-gen3-cpg.c clk: renesas: rcar-gen3: Remove unused variable 2019-04-11 10:35:45 -07:00
rcar-gen3-cpg.h Merge branches 'clk-stm32f4', 'clk-tegra', 'clk-at91', 'clk-sifive-fu540' and 'clk-spdx' into clk-next 2019-05-07 11:45:29 -07:00
rcar-usb2-clock-sel.c clk: Remove io.h from clk-provider.h 2019-05-15 13:21:37 -07:00
renesas-cpg-mssr.c clk: renesas: cpg-mssr: Fix reset control race condition 2019-07-22 15:04:54 -07:00
renesas-cpg-mssr.h clk: renesas: Use the correct style for SPDX License Identifier 2019-05-01 13:01:18 -07:00