forked from Minki/linux
e2eaa339af
Perform a mechanical translation of rd88f6281-setup.c into DT. Since the hardware differs between the A0 and A1 stepping, two dts files are used, and a .dtsi file for the common parts. The A0 part does not have a "wan" port on the switch and uses PHY address 10 to address the switch. The A1 part does have the "wan" port and uses address 0. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
153 lines
2.2 KiB
Plaintext
153 lines
2.2 KiB
Plaintext
/*
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* Marvell RD88F6181 Common Board descrition
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*
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* Andrew Lunn <andrew@lunn.ch>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*
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* This file contains the definitions that are common between the two
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* variants of the Marvell Kirkwood Development Board.
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*/
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#include "kirkwood.dtsi"
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#include "kirkwood-6281.dtsi"
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/ {
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memory {
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device_type = "memory";
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reg = <0x00000000 0x20000000>;
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};
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chosen {
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bootargs = "console=ttyS0,115200n8";
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};
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mbus {
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pcie-controller {
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status = "okay";
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pcie@1,0 {
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status = "okay";
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};
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};
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};
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ocp@f1000000 {
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pinctrl: pinctrl@10000 {
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pinctrl-0 = <&pmx_sdio_cd>;
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pinctrl-names = "default";
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pmx_sdio_cd: pmx-sdio-cd {
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marvell,pins = "mpp28";
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marvell,function = "gpio";
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};
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};
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serial@12000 {
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status = "okay";
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};
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sata@80000 {
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status = "okay";
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nr-ports = <2>;
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};
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mvsdio@90000 {
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pinctrl-0 = <&pmx_sdio &pmx_sdio_cd>;
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pinctrl-names = "default";
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status = "okay";
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cd-gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>;
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/* No WP GPIO */
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};
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};
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dsa@0 {
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compatible = "marvell,dsa";
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#address-cells = <2>;
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#size-cells = <0>;
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dsa,ethernet = <ð0>;
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dsa,mii-bus = <ðphy1>;
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switch@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "lan1";
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};
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port@1 {
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reg = <1>;
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label = "lan2";
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};
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port@2 {
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reg = <2>;
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label = "lan3";
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};
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port@3 {
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reg = <3>;
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label = "lan4";
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};
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port@5 {
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reg = <5>;
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label = "cpu";
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};
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};
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};
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};
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&nand {
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status = "okay";
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partition@0 {
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label = "u-boot";
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reg = <0x0000000 0x100000>;
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read-only;
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};
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partition@100000 {
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label = "uImage";
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reg = <0x0100000 0x200000>;
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};
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partition@300000 {
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label = "data";
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reg = <0x0300000 0x500000>;
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};
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};
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&mdio {
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status = "okay";
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ethphy0: ethernet-phy@0 {
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reg = <0>;
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};
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ethphy1: ethernet-phy@ff {
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reg = <0xff>; /* No PHY attached */
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speed = <1000>;
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duple = <1>;
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};
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};
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ð0 {
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status = "okay";
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ethernet0-port@0 {
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phy-handle = <ðphy0>;
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};
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};
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ð1 {
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status = "okay";
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ethernet1-port@0 {
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phy-handle = <ðphy1>;
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};
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};
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