forked from Minki/linux
7a88d62862
Add switch specific domain routines required for 16-bit routing support in switches with hierarchical implementation of routing tables. Signed-off-by: Alexandre Bounine <alexandre.bounine@idt.com> Cc: Matt Porter <mporter@kernel.crashing.org> Cc: Li Yang <leoli@freescale.com> Cc: Kumar Gala <galak@kernel.crashing.org> Cc: Thomas Moll <thomas.moll@sysgo.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
316 lines
9.2 KiB
C
316 lines
9.2 KiB
C
/*
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* RapidIO Tsi57x switch family support
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*
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* Copyright 2009-2010 Integrated Device Technology, Inc.
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* Alexandre Bounine <alexandre.bounine@idt.com>
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* - Added EM support
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* - Modified switch operations initialization.
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*
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* Copyright 2005 MontaVista Software, Inc.
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* Matt Porter <mporter@kernel.crashing.org>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/rio.h>
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#include <linux/rio_drv.h>
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#include <linux/rio_ids.h>
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#include <linux/delay.h>
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#include "../rio.h"
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/* Global (broadcast) route registers */
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#define SPBC_ROUTE_CFG_DESTID 0x10070
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#define SPBC_ROUTE_CFG_PORT 0x10074
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/* Per port route registers */
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#define SPP_ROUTE_CFG_DESTID(n) (0x11070 + 0x100*n)
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#define SPP_ROUTE_CFG_PORT(n) (0x11074 + 0x100*n)
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#define TSI578_SP_MODE(n) (0x11004 + n*0x100)
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#define TSI578_SP_MODE_GLBL 0x10004
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#define TSI578_SP_MODE_PW_DIS 0x08000000
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#define TSI578_SP_MODE_LUT_512 0x01000000
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#define TSI578_SP_CTL_INDEP(n) (0x13004 + n*0x100)
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#define TSI578_SP_LUT_PEINF(n) (0x13010 + n*0x100)
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#define TSI578_SP_CS_TX(n) (0x13014 + n*0x100)
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#define TSI578_SP_INT_STATUS(n) (0x13018 + n*0x100)
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#define TSI578_GLBL_ROUTE_BASE 0x10078
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static int
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tsi57x_route_add_entry(struct rio_mport *mport, u16 destid, u8 hopcount,
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u16 table, u16 route_destid, u8 route_port)
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{
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if (table == RIO_GLOBAL_TABLE) {
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rio_mport_write_config_32(mport, destid, hopcount,
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SPBC_ROUTE_CFG_DESTID, route_destid);
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rio_mport_write_config_32(mport, destid, hopcount,
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SPBC_ROUTE_CFG_PORT, route_port);
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} else {
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rio_mport_write_config_32(mport, destid, hopcount,
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SPP_ROUTE_CFG_DESTID(table), route_destid);
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rio_mport_write_config_32(mport, destid, hopcount,
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SPP_ROUTE_CFG_PORT(table), route_port);
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}
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udelay(10);
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return 0;
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}
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static int
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tsi57x_route_get_entry(struct rio_mport *mport, u16 destid, u8 hopcount,
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u16 table, u16 route_destid, u8 *route_port)
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{
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int ret = 0;
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u32 result;
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if (table == RIO_GLOBAL_TABLE) {
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/* Use local RT of the ingress port to avoid possible
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race condition */
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rio_mport_read_config_32(mport, destid, hopcount,
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RIO_SWP_INFO_CAR, &result);
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table = (result & RIO_SWP_INFO_PORT_NUM_MASK);
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}
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rio_mport_write_config_32(mport, destid, hopcount,
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SPP_ROUTE_CFG_DESTID(table), route_destid);
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rio_mport_read_config_32(mport, destid, hopcount,
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SPP_ROUTE_CFG_PORT(table), &result);
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*route_port = (u8)result;
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if (*route_port > 15)
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ret = -1;
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return ret;
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}
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static int
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tsi57x_route_clr_table(struct rio_mport *mport, u16 destid, u8 hopcount,
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u16 table)
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{
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u32 route_idx;
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u32 lut_size;
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lut_size = (mport->sys_size) ? 0x1ff : 0xff;
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if (table == RIO_GLOBAL_TABLE) {
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rio_mport_write_config_32(mport, destid, hopcount,
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SPBC_ROUTE_CFG_DESTID, 0x80000000);
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for (route_idx = 0; route_idx <= lut_size; route_idx++)
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rio_mport_write_config_32(mport, destid, hopcount,
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SPBC_ROUTE_CFG_PORT,
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RIO_INVALID_ROUTE);
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} else {
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rio_mport_write_config_32(mport, destid, hopcount,
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SPP_ROUTE_CFG_DESTID(table), 0x80000000);
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for (route_idx = 0; route_idx <= lut_size; route_idx++)
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rio_mport_write_config_32(mport, destid, hopcount,
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SPP_ROUTE_CFG_PORT(table) , RIO_INVALID_ROUTE);
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}
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return 0;
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}
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static int
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tsi57x_set_domain(struct rio_mport *mport, u16 destid, u8 hopcount,
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u8 sw_domain)
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{
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u32 regval;
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/*
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* Switch domain configuration operates only at global level
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*/
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/* Turn off flat (LUT_512) mode */
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rio_mport_read_config_32(mport, destid, hopcount,
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TSI578_SP_MODE_GLBL, ®val);
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rio_mport_write_config_32(mport, destid, hopcount, TSI578_SP_MODE_GLBL,
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regval & ~TSI578_SP_MODE_LUT_512);
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/* Set switch domain base */
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rio_mport_write_config_32(mport, destid, hopcount,
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TSI578_GLBL_ROUTE_BASE,
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(u32)(sw_domain << 24));
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return 0;
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}
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static int
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tsi57x_get_domain(struct rio_mport *mport, u16 destid, u8 hopcount,
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u8 *sw_domain)
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{
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u32 regval;
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/*
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* Switch domain configuration operates only at global level
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*/
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rio_mport_read_config_32(mport, destid, hopcount,
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TSI578_GLBL_ROUTE_BASE, ®val);
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*sw_domain = (u8)(regval >> 24);
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return 0;
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}
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static int
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tsi57x_em_init(struct rio_dev *rdev)
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{
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struct rio_mport *mport = rdev->net->hport;
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u16 destid = rdev->rswitch->destid;
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u8 hopcount = rdev->rswitch->hopcount;
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u32 regval;
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int portnum;
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pr_debug("TSI578 %s [%d:%d]\n", __func__, destid, hopcount);
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for (portnum = 0; portnum < 16; portnum++) {
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/* Make sure that Port-Writes are enabled (for all ports) */
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rio_mport_read_config_32(mport, destid, hopcount,
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TSI578_SP_MODE(portnum), ®val);
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rio_mport_write_config_32(mport, destid, hopcount,
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TSI578_SP_MODE(portnum),
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regval & ~TSI578_SP_MODE_PW_DIS);
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/* Clear all pending interrupts */
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rio_mport_read_config_32(mport, destid, hopcount,
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rdev->phys_efptr +
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RIO_PORT_N_ERR_STS_CSR(portnum),
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®val);
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rio_mport_write_config_32(mport, destid, hopcount,
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rdev->phys_efptr +
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RIO_PORT_N_ERR_STS_CSR(portnum),
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regval & 0x07120214);
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rio_mport_read_config_32(mport, destid, hopcount,
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TSI578_SP_INT_STATUS(portnum), ®val);
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rio_mport_write_config_32(mport, destid, hopcount,
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TSI578_SP_INT_STATUS(portnum),
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regval & 0x000700bd);
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/* Enable all interrupts to allow ports to send a port-write */
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rio_mport_read_config_32(mport, destid, hopcount,
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TSI578_SP_CTL_INDEP(portnum), ®val);
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rio_mport_write_config_32(mport, destid, hopcount,
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TSI578_SP_CTL_INDEP(portnum),
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regval | 0x000b0000);
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/* Skip next (odd) port if the current port is in x4 mode */
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rio_mport_read_config_32(mport, destid, hopcount,
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rdev->phys_efptr + RIO_PORT_N_CTL_CSR(portnum),
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®val);
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if ((regval & RIO_PORT_N_CTL_PWIDTH) == RIO_PORT_N_CTL_PWIDTH_4)
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portnum++;
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}
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return 0;
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}
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static int
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tsi57x_em_handler(struct rio_dev *rdev, u8 portnum)
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{
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struct rio_mport *mport = rdev->net->hport;
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u16 destid = rdev->rswitch->destid;
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u8 hopcount = rdev->rswitch->hopcount;
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u32 intstat, err_status;
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int sendcount, checkcount;
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u8 route_port;
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u32 regval;
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rio_mport_read_config_32(mport, destid, hopcount,
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rdev->phys_efptr + RIO_PORT_N_ERR_STS_CSR(portnum),
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&err_status);
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if ((err_status & RIO_PORT_N_ERR_STS_PORT_OK) &&
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(err_status & (RIO_PORT_N_ERR_STS_PW_OUT_ES |
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RIO_PORT_N_ERR_STS_PW_INP_ES))) {
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/* Remove any queued packets by locking/unlocking port */
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rio_mport_read_config_32(mport, destid, hopcount,
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rdev->phys_efptr + RIO_PORT_N_CTL_CSR(portnum),
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®val);
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if (!(regval & RIO_PORT_N_CTL_LOCKOUT)) {
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rio_mport_write_config_32(mport, destid, hopcount,
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rdev->phys_efptr + RIO_PORT_N_CTL_CSR(portnum),
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regval | RIO_PORT_N_CTL_LOCKOUT);
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udelay(50);
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rio_mport_write_config_32(mport, destid, hopcount,
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rdev->phys_efptr + RIO_PORT_N_CTL_CSR(portnum),
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regval);
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}
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/* Read from link maintenance response register to clear
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* valid bit
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*/
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rio_mport_read_config_32(mport, destid, hopcount,
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rdev->phys_efptr + RIO_PORT_N_MNT_RSP_CSR(portnum),
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®val);
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/* Send a Packet-Not-Accepted/Link-Request-Input-Status control
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* symbol to recover from IES/OES
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*/
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sendcount = 3;
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while (sendcount) {
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rio_mport_write_config_32(mport, destid, hopcount,
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TSI578_SP_CS_TX(portnum), 0x40fc8000);
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checkcount = 3;
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while (checkcount--) {
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udelay(50);
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rio_mport_read_config_32(
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mport, destid, hopcount,
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rdev->phys_efptr +
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RIO_PORT_N_MNT_RSP_CSR(portnum),
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®val);
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if (regval & RIO_PORT_N_MNT_RSP_RVAL)
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goto exit_es;
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}
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sendcount--;
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}
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}
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exit_es:
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/* Clear implementation specific error status bits */
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rio_mport_read_config_32(mport, destid, hopcount,
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TSI578_SP_INT_STATUS(portnum), &intstat);
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pr_debug("TSI578[%x:%x] SP%d_INT_STATUS=0x%08x\n",
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destid, hopcount, portnum, intstat);
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if (intstat & 0x10000) {
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rio_mport_read_config_32(mport, destid, hopcount,
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TSI578_SP_LUT_PEINF(portnum), ®val);
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regval = (mport->sys_size) ? (regval >> 16) : (regval >> 24);
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route_port = rdev->rswitch->route_table[regval];
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pr_debug("RIO: TSI578[%s] P%d LUT Parity Error (destID=%d)\n",
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rio_name(rdev), portnum, regval);
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tsi57x_route_add_entry(mport, destid, hopcount,
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RIO_GLOBAL_TABLE, regval, route_port);
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}
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rio_mport_write_config_32(mport, destid, hopcount,
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TSI578_SP_INT_STATUS(portnum),
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intstat & 0x000700bd);
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return 0;
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}
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static int tsi57x_switch_init(struct rio_dev *rdev, int do_enum)
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{
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pr_debug("RIO: %s for %s\n", __func__, rio_name(rdev));
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rdev->rswitch->add_entry = tsi57x_route_add_entry;
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rdev->rswitch->get_entry = tsi57x_route_get_entry;
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rdev->rswitch->clr_table = tsi57x_route_clr_table;
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rdev->rswitch->set_domain = tsi57x_set_domain;
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rdev->rswitch->get_domain = tsi57x_get_domain;
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rdev->rswitch->em_init = tsi57x_em_init;
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rdev->rswitch->em_handle = tsi57x_em_handler;
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return 0;
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}
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DECLARE_RIO_SWITCH_INIT(RIO_VID_TUNDRA, RIO_DID_TSI572, tsi57x_switch_init);
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DECLARE_RIO_SWITCH_INIT(RIO_VID_TUNDRA, RIO_DID_TSI574, tsi57x_switch_init);
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DECLARE_RIO_SWITCH_INIT(RIO_VID_TUNDRA, RIO_DID_TSI577, tsi57x_switch_init);
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DECLARE_RIO_SWITCH_INIT(RIO_VID_TUNDRA, RIO_DID_TSI578, tsi57x_switch_init);
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