57155c6523
SH3/4 (with MMU) have a virtually indexed cache, requiring explicit work to avoid consistency problems arising from having the same physical address range cached in multiple cache lines. This is unneeded for the NOMMU case, and some of the resulting code paths (kmap_coherent) don't work. SH2 only avoided this problem by having a 4-way associative cache with way size equal to the page size (4k), yielding no cache index bits outside of the page offset and thus no aliases. Signed-off-by: Rich Felker <dalias@libc.org> |
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| .. | ||
| irq | ||
| sh2 | ||
| sh2a | ||
| sh3 | ||
| sh4 | ||
| sh4a | ||
| sh5 | ||
| shmobile | ||
| adc.c | ||
| clock-cpg.c | ||
| clock.c | ||
| fpu.c | ||
| init.c | ||
| Makefile | ||
| pfc.c | ||
| proc.c | ||