Palmer Dabbelt 566d6c428e RISC-V: Don't set cacheinfo.{physical_line_partition,attributes} ... These are just hard coded in the RISC-V port, which doesn't make any sense. We should probably be setting these from device tree entries when they exist, but for now I think it's saner to just leave them all as their default values. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Jeremy Linton <jeremy.linton@arm.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>		2018-10-22 17:03:35 -07:00
..
configs	irqchip: add a SiFive PLIC driver	2018-08-13 08:31:32 -07:00
include	RISC-V: include linux/ftrace.h in asm-prototypes.h	2018-09-24 13:12:27 -07:00
kernel	RISC-V: Don't set cacheinfo.{physical_line_partition,attributes}	2018-10-22 17:03:35 -07:00
lib	RISC-V: implement __lshrti3.	2018-08-13 08:31:30 -07:00
mm	mm: convert return type of handle_mm_fault() caller to vm_fault_t	2018-08-17 16:20:28 -07:00
Kconfig	kconfig: include kernel/Kconfig.preempt from init/Kconfig	2018-08-02 08:06:54 +09:00
Kconfig.debug	Kconfig: consolidate the "Kernel hacking" menu	2018-08-02 08:06:48 +09:00
Makefile	kbuild: rename LDFLAGS to KBUILD_LDFLAGS	2018-08-24 08:22:08 +09:00