b24413180f
Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of the kernel, which is GPL version 2. Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. How this work was done: Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information, Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords. The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files. The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation. Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines). All documentation files were explicitly excluded. The following heuristics were used to determine which SPDX license identifiers to apply. - when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied. For non */uapi/* files that summary was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139 and resulted in the first patch in this series. If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930 and resulted in the second patch in this series. - if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary: SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1 and that resulted in the third patch in this series. - when the two scanners agreed on the detected license(s), that became the concluded license(s). - when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred. - In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics). - When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation. - If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time. In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation. Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related. Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files. In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier. Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified. These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches. Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
316 lines
15 KiB
C
316 lines
15 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _M32102_H_
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#define _M32102_H_
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/*
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* Renesas M32R 32102 group
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*
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* Copyright (c) 2001 Hitoshi Yamamoto
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* Copyright (c) 2003, 2004 Renesas Technology Corp.
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*/
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/*======================================================================*
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* Special Function Register
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*======================================================================*/
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#if !defined(CONFIG_CHIP_M32104)
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#define M32R_SFR_OFFSET (0x00E00000) /* 0x00E00000-0x00EFFFFF 1[MB] */
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#else
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#define M32R_SFR_OFFSET (0x00700000) /* 0x00700000-0x007FFFFF 1[MB] */
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#endif
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/*
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* Clock and Power Management registers.
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*/
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#define M32R_CPM_OFFSET (0x000F4000+M32R_SFR_OFFSET)
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#define M32R_CPM_CPUCLKCR_PORTL (0x00+M32R_CPM_OFFSET)
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#define M32R_CPM_CLKMOD_PORTL (0x04+M32R_CPM_OFFSET)
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#define M32R_CPM_PLLCR_PORTL (0x08+M32R_CPM_OFFSET)
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/*
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* DMA Controller registers.
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*/
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#define M32R_DMA_OFFSET (0x000F8000+M32R_SFR_OFFSET)
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#define M32R_DMAEN_PORTL (0x000+M32R_DMA_OFFSET)
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#define M32R_DMAISTS_PORTL (0x004+M32R_DMA_OFFSET)
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#define M32R_DMAEDET_PORTL (0x008+M32R_DMA_OFFSET)
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#define M32R_DMAASTS_PORTL (0x00c+M32R_DMA_OFFSET)
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#define M32R_DMA0CR0_PORTL (0x100+M32R_DMA_OFFSET)
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#define M32R_DMA0CR1_PORTL (0x104+M32R_DMA_OFFSET)
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#define M32R_DMA0CSA_PORTL (0x108+M32R_DMA_OFFSET)
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#define M32R_DMA0RSA_PORTL (0x10c+M32R_DMA_OFFSET)
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#define M32R_DMA0CDA_PORTL (0x110+M32R_DMA_OFFSET)
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#define M32R_DMA0RDA_PORTL (0x114+M32R_DMA_OFFSET)
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#define M32R_DMA0CBCUT_PORTL (0x118+M32R_DMA_OFFSET)
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#define M32R_DMA0RBCUT_PORTL (0x11c+M32R_DMA_OFFSET)
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#define M32R_DMA1CR0_PORTL (0x200+M32R_DMA_OFFSET)
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#define M32R_DMA1CR1_PORTL (0x204+M32R_DMA_OFFSET)
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#define M32R_DMA1CSA_PORTL (0x208+M32R_DMA_OFFSET)
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#define M32R_DMA1RSA_PORTL (0x20c+M32R_DMA_OFFSET)
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#define M32R_DMA1CDA_PORTL (0x210+M32R_DMA_OFFSET)
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#define M32R_DMA1RDA_PORTL (0x214+M32R_DMA_OFFSET)
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#define M32R_DMA1CBCUT_PORTL (0x218+M32R_DMA_OFFSET)
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#define M32R_DMA1RBCUT_PORTL (0x21c+M32R_DMA_OFFSET)
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/*
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* Multi Function Timer registers.
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*/
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#define M32R_MFT_OFFSET (0x000FC000+M32R_SFR_OFFSET)
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#define M32R_MFTCR_PORTL (0x000+M32R_MFT_OFFSET) /* MFT control */
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#define M32R_MFTRPR_PORTL (0x004+M32R_MFT_OFFSET) /* MFT real port */
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#define M32R_MFT0_OFFSET (0x100+M32R_MFT_OFFSET)
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#define M32R_MFT0MOD_PORTL (0x00+M32R_MFT0_OFFSET) /* MFT0 mode */
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#define M32R_MFT0BOS_PORTL (0x04+M32R_MFT0_OFFSET) /* MFT0 b-port output status */
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#define M32R_MFT0CUT_PORTL (0x08+M32R_MFT0_OFFSET) /* MFT0 count */
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#define M32R_MFT0RLD_PORTL (0x0C+M32R_MFT0_OFFSET) /* MFT0 reload */
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#define M32R_MFT0CMPRLD_PORTL (0x10+M32R_MFT0_OFFSET) /* MFT0 compare reload */
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#define M32R_MFT1_OFFSET (0x200+M32R_MFT_OFFSET)
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#define M32R_MFT1MOD_PORTL (0x00+M32R_MFT1_OFFSET) /* MFT1 mode */
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#define M32R_MFT1BOS_PORTL (0x04+M32R_MFT1_OFFSET) /* MFT1 b-port output status */
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#define M32R_MFT1CUT_PORTL (0x08+M32R_MFT1_OFFSET) /* MFT1 count */
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#define M32R_MFT1RLD_PORTL (0x0C+M32R_MFT1_OFFSET) /* MFT1 reload */
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#define M32R_MFT1CMPRLD_PORTL (0x10+M32R_MFT1_OFFSET) /* MFT1 compare reload */
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#define M32R_MFT2_OFFSET (0x300+M32R_MFT_OFFSET)
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#define M32R_MFT2MOD_PORTL (0x00+M32R_MFT2_OFFSET) /* MFT2 mode */
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#define M32R_MFT2BOS_PORTL (0x04+M32R_MFT2_OFFSET) /* MFT2 b-port output status */
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#define M32R_MFT2CUT_PORTL (0x08+M32R_MFT2_OFFSET) /* MFT2 count */
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#define M32R_MFT2RLD_PORTL (0x0C+M32R_MFT2_OFFSET) /* MFT2 reload */
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#define M32R_MFT2CMPRLD_PORTL (0x10+M32R_MFT2_OFFSET) /* MFT2 compare reload */
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#define M32R_MFT3_OFFSET (0x400+M32R_MFT_OFFSET)
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#define M32R_MFT3MOD_PORTL (0x00+M32R_MFT3_OFFSET) /* MFT3 mode */
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#define M32R_MFT3BOS_PORTL (0x04+M32R_MFT3_OFFSET) /* MFT3 b-port output status */
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#define M32R_MFT3CUT_PORTL (0x08+M32R_MFT3_OFFSET) /* MFT3 count */
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#define M32R_MFT3RLD_PORTL (0x0C+M32R_MFT3_OFFSET) /* MFT3 reload */
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#define M32R_MFT3CMPRLD_PORTL (0x10+M32R_MFT3_OFFSET) /* MFT3 compare reload */
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#define M32R_MFT4_OFFSET (0x500+M32R_MFT_OFFSET)
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#define M32R_MFT4MOD_PORTL (0x00+M32R_MFT4_OFFSET) /* MFT4 mode */
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#define M32R_MFT4BOS_PORTL (0x04+M32R_MFT4_OFFSET) /* MFT4 b-port output status */
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#define M32R_MFT4CUT_PORTL (0x08+M32R_MFT4_OFFSET) /* MFT4 count */
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#define M32R_MFT4RLD_PORTL (0x0C+M32R_MFT4_OFFSET) /* MFT4 reload */
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#define M32R_MFT4CMPRLD_PORTL (0x10+M32R_MFT4_OFFSET) /* MFT4 compare reload */
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#define M32R_MFT5_OFFSET (0x600+M32R_MFT_OFFSET)
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#define M32R_MFT5MOD_PORTL (0x00+M32R_MFT5_OFFSET) /* MFT4 mode */
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#define M32R_MFT5BOS_PORTL (0x04+M32R_MFT5_OFFSET) /* MFT4 b-port output status */
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#define M32R_MFT5CUT_PORTL (0x08+M32R_MFT5_OFFSET) /* MFT4 count */
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#define M32R_MFT5RLD_PORTL (0x0C+M32R_MFT5_OFFSET) /* MFT4 reload */
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#define M32R_MFT5CMPRLD_PORTL (0x10+M32R_MFT5_OFFSET) /* MFT4 compare reload */
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#if (defined(CONFIG_CHIP_M32700) && !defined(CONFIG_PLAT_MAPPI2)) \
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|| defined(CONFIG_CHIP_M32104)
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#define M32R_MFTCR_MFT0MSK (1UL<<31) /* b0 */
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#define M32R_MFTCR_MFT1MSK (1UL<<30) /* b1 */
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#define M32R_MFTCR_MFT2MSK (1UL<<29) /* b2 */
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#define M32R_MFTCR_MFT3MSK (1UL<<28) /* b3 */
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#define M32R_MFTCR_MFT4MSK (1UL<<27) /* b4 */
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#define M32R_MFTCR_MFT5MSK (1UL<<26) /* b5 */
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#define M32R_MFTCR_MFT0EN (1UL<<23) /* b8 */
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#define M32R_MFTCR_MFT1EN (1UL<<22) /* b9 */
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#define M32R_MFTCR_MFT2EN (1UL<<21) /* b10 */
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#define M32R_MFTCR_MFT3EN (1UL<<20) /* b11 */
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#define M32R_MFTCR_MFT4EN (1UL<<19) /* b12 */
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#define M32R_MFTCR_MFT5EN (1UL<<18) /* b13 */
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#else
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#define M32R_MFTCR_MFT0MSK (1UL<<15) /* b16 */
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#define M32R_MFTCR_MFT1MSK (1UL<<14) /* b17 */
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#define M32R_MFTCR_MFT2MSK (1UL<<13) /* b18 */
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#define M32R_MFTCR_MFT3MSK (1UL<<12) /* b19 */
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#define M32R_MFTCR_MFT4MSK (1UL<<11) /* b20 */
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#define M32R_MFTCR_MFT5MSK (1UL<<10) /* b21 */
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#define M32R_MFTCR_MFT0EN (1UL<<7) /* b24 */
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#define M32R_MFTCR_MFT1EN (1UL<<6) /* b25 */
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#define M32R_MFTCR_MFT2EN (1UL<<5) /* b26 */
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#define M32R_MFTCR_MFT3EN (1UL<<4) /* b27 */
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#define M32R_MFTCR_MFT4EN (1UL<<3) /* b28 */
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#define M32R_MFTCR_MFT5EN (1UL<<2) /* b29 */
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#endif
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#define M32R_MFTMOD_CC_MASK (1UL<<15) /* b16 */
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#define M32R_MFTMOD_TCCR (1UL<<13) /* b18 */
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#define M32R_MFTMOD_GTSEL000 (0UL<<8) /* b21-23 : 000 */
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#define M32R_MFTMOD_GTSEL001 (1UL<<8) /* b21-23 : 001 */
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#define M32R_MFTMOD_GTSEL010 (2UL<<8) /* b21-23 : 010 */
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#define M32R_MFTMOD_GTSEL011 (3UL<<8) /* b21-23 : 011 */
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#define M32R_MFTMOD_GTSEL110 (6UL<<8) /* b21-23 : 110 */
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#define M32R_MFTMOD_GTSEL111 (7UL<<8) /* b21-23 : 111 */
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#define M32R_MFTMOD_CMSEL (1UL<<3) /* b28 */
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#define M32R_MFTMOD_CSSEL000 (0UL<<0) /* b29-b31 : 000 */
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#define M32R_MFTMOD_CSSEL001 (1UL<<0) /* b29-b31 : 001 */
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#define M32R_MFTMOD_CSSEL010 (2UL<<0) /* b29-b31 : 010 */
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#define M32R_MFTMOD_CSSEL011 (3UL<<0) /* b29-b31 : 011 */
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#define M32R_MFTMOD_CSSEL100 (4UL<<0) /* b29-b31 : 100 */
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#define M32R_MFTMOD_CSSEL110 (6UL<<0) /* b29-b31 : 110 */
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/*
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* Serial I/O registers.
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*/
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#define M32R_SIO_OFFSET (0x000FD000+M32R_SFR_OFFSET)
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#define M32R_SIO0_CR_PORTL (0x000+M32R_SIO_OFFSET)
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#define M32R_SIO0_MOD0_PORTL (0x004+M32R_SIO_OFFSET)
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#define M32R_SIO0_MOD1_PORTL (0x008+M32R_SIO_OFFSET)
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#define M32R_SIO0_STS_PORTL (0x00C+M32R_SIO_OFFSET)
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#define M32R_SIO0_TRCR_PORTL (0x010+M32R_SIO_OFFSET)
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#define M32R_SIO0_BAUR_PORTL (0x014+M32R_SIO_OFFSET)
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#define M32R_SIO0_RBAUR_PORTL (0x018+M32R_SIO_OFFSET)
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#define M32R_SIO0_TXB_PORTL (0x01C+M32R_SIO_OFFSET)
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#define M32R_SIO0_RXB_PORTL (0x020+M32R_SIO_OFFSET)
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/*
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* Interrupt Control Unit registers.
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*/
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#define M32R_ICU_OFFSET (0x000FF000+M32R_SFR_OFFSET)
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#define M32R_ICU_ISTS_PORTL (0x004+M32R_ICU_OFFSET)
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#define M32R_ICU_IREQ0_PORTL (0x008+M32R_ICU_OFFSET)
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#define M32R_ICU_IREQ1_PORTL (0x00C+M32R_ICU_OFFSET)
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#define M32R_ICU_SBICR_PORTL (0x018+M32R_ICU_OFFSET)
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#define M32R_ICU_IMASK_PORTL (0x01C+M32R_ICU_OFFSET)
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#define M32R_ICU_CR1_PORTL (0x200+M32R_ICU_OFFSET) /* INT0 */
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#define M32R_ICU_CR2_PORTL (0x204+M32R_ICU_OFFSET) /* INT1 */
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#define M32R_ICU_CR3_PORTL (0x208+M32R_ICU_OFFSET) /* INT2 */
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#define M32R_ICU_CR4_PORTL (0x20C+M32R_ICU_OFFSET) /* INT3 */
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#define M32R_ICU_CR5_PORTL (0x210+M32R_ICU_OFFSET) /* INT4 */
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#define M32R_ICU_CR6_PORTL (0x214+M32R_ICU_OFFSET) /* INT5 */
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#define M32R_ICU_CR7_PORTL (0x218+M32R_ICU_OFFSET) /* INT6 */
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#define M32R_ICU_CR8_PORTL (0x219+M32R_ICU_OFFSET) /* INT7 */
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#define M32R_ICU_CR16_PORTL (0x23C+M32R_ICU_OFFSET) /* MFT0 */
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#define M32R_ICU_CR17_PORTL (0x240+M32R_ICU_OFFSET) /* MFT1 */
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#define M32R_ICU_CR18_PORTL (0x244+M32R_ICU_OFFSET) /* MFT2 */
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#define M32R_ICU_CR19_PORTL (0x248+M32R_ICU_OFFSET) /* MFT3 */
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#define M32R_ICU_CR20_PORTL (0x24C+M32R_ICU_OFFSET) /* MFT4 */
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#define M32R_ICU_CR21_PORTL (0x250+M32R_ICU_OFFSET) /* MFT5 */
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#define M32R_ICU_CR32_PORTL (0x27C+M32R_ICU_OFFSET) /* DMA0 */
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#define M32R_ICU_CR33_PORTL (0x280+M32R_ICU_OFFSET) /* DMA1 */
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#define M32R_ICU_CR48_PORTL (0x2BC+M32R_ICU_OFFSET) /* SIO0 */
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#define M32R_ICU_CR49_PORTL (0x2C0+M32R_ICU_OFFSET) /* SIO0 */
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#define M32R_ICU_CR50_PORTL (0x2C4+M32R_ICU_OFFSET) /* SIO1 */
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#define M32R_ICU_CR51_PORTL (0x2C8+M32R_ICU_OFFSET) /* SIO1 */
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#define M32R_ICU_CR52_PORTL (0x2CC+M32R_ICU_OFFSET) /* SIO2 */
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#define M32R_ICU_CR53_PORTL (0x2D0+M32R_ICU_OFFSET) /* SIO2 */
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#define M32R_ICU_CR54_PORTL (0x2D4+M32R_ICU_OFFSET) /* SIO3 */
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#define M32R_ICU_CR55_PORTL (0x2D8+M32R_ICU_OFFSET) /* SIO3 */
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#define M32R_ICU_CR56_PORTL (0x2DC+M32R_ICU_OFFSET) /* SIO4 */
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#define M32R_ICU_CR57_PORTL (0x2E0+M32R_ICU_OFFSET) /* SIO4 */
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#ifdef CONFIG_SMP
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#define M32R_ICU_IPICR0_PORTL (0x2dc+M32R_ICU_OFFSET) /* IPI0 */
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#define M32R_ICU_IPICR1_PORTL (0x2e0+M32R_ICU_OFFSET) /* IPI1 */
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#define M32R_ICU_IPICR2_PORTL (0x2e4+M32R_ICU_OFFSET) /* IPI2 */
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#define M32R_ICU_IPICR3_PORTL (0x2e8+M32R_ICU_OFFSET) /* IPI3 */
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#define M32R_ICU_IPICR4_PORTL (0x2ec+M32R_ICU_OFFSET) /* IPI4 */
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#define M32R_ICU_IPICR5_PORTL (0x2f0+M32R_ICU_OFFSET) /* IPI5 */
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#define M32R_ICU_IPICR6_PORTL (0x2f4+M32R_ICU_OFFSET) /* IPI6 */
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#define M32R_ICU_IPICR7_PORTL (0x2f8+M32R_ICU_OFFSET) /* IPI7 */
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#endif /* CONFIG_SMP */
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#define M32R_ICUIMASK_IMSK0 (0UL<<16) /* b13-b15: Disable interrupt */
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#define M32R_ICUIMASK_IMSK1 (1UL<<16) /* b13-b15: Enable level 0 interrupt */
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#define M32R_ICUIMASK_IMSK2 (2UL<<16) /* b13-b15: Enable level 0,1 interrupt */
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#define M32R_ICUIMASK_IMSK3 (3UL<<16) /* b13-b15: Enable level 0-2 interrupt */
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#define M32R_ICUIMASK_IMSK4 (4UL<<16) /* b13-b15: Enable level 0-3 interrupt */
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#define M32R_ICUIMASK_IMSK5 (5UL<<16) /* b13-b15: Enable level 0-4 interrupt */
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#define M32R_ICUIMASK_IMSK6 (6UL<<16) /* b13-b15: Enable level 0-5 interrupt */
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#define M32R_ICUIMASK_IMSK7 (7UL<<16) /* b13-b15: Enable level 0-6 interrupt */
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#define M32R_ICUCR_IEN (1UL<<12) /* b19: Interrupt enable */
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#define M32R_ICUCR_IRQ (1UL<<8) /* b23: Interrupt request */
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#define M32R_ICUCR_ISMOD00 (0UL<<4) /* b26-b27: Interrupt sense mode Edge HtoL */
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#define M32R_ICUCR_ISMOD01 (1UL<<4) /* b26-b27: Interrupt sense mode Level L */
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#define M32R_ICUCR_ISMOD10 (2UL<<4) /* b26-b27: Interrupt sense mode Edge LtoH*/
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#define M32R_ICUCR_ISMOD11 (3UL<<4) /* b26-b27: Interrupt sense mode Level H */
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#define M32R_ICUCR_ILEVEL0 (0UL<<0) /* b29-b31: Interrupt priority level 0 */
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#define M32R_ICUCR_ILEVEL1 (1UL<<0) /* b29-b31: Interrupt priority level 1 */
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#define M32R_ICUCR_ILEVEL2 (2UL<<0) /* b29-b31: Interrupt priority level 2 */
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#define M32R_ICUCR_ILEVEL3 (3UL<<0) /* b29-b31: Interrupt priority level 3 */
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#define M32R_ICUCR_ILEVEL4 (4UL<<0) /* b29-b31: Interrupt priority level 4 */
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#define M32R_ICUCR_ILEVEL5 (5UL<<0) /* b29-b31: Interrupt priority level 5 */
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#define M32R_ICUCR_ILEVEL6 (6UL<<0) /* b29-b31: Interrupt priority level 6 */
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#define M32R_ICUCR_ILEVEL7 (7UL<<0) /* b29-b31: Disable interrupt */
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#define M32R_IRQ_INT0 (1) /* INT0 */
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#define M32R_IRQ_INT1 (2) /* INT1 */
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#define M32R_IRQ_INT2 (3) /* INT2 */
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#define M32R_IRQ_INT3 (4) /* INT3 */
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#define M32R_IRQ_INT4 (5) /* INT4 */
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#define M32R_IRQ_INT5 (6) /* INT5 */
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#define M32R_IRQ_INT6 (7) /* INT6 */
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#define M32R_IRQ_MFT0 (16) /* MFT0 */
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#define M32R_IRQ_MFT1 (17) /* MFT1 */
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#define M32R_IRQ_MFT2 (18) /* MFT2 */
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#define M32R_IRQ_MFT3 (19) /* MFT3 */
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#ifdef CONFIG_CHIP_M32104
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#define M32R_IRQ_MFTX0 (24) /* MFTX0 */
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#define M32R_IRQ_MFTX1 (25) /* MFTX1 */
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#define M32R_IRQ_DMA0 (32) /* DMA0 */
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#define M32R_IRQ_DMA1 (33) /* DMA1 */
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#define M32R_IRQ_DMA2 (34) /* DMA2 */
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#define M32R_IRQ_DMA3 (35) /* DMA3 */
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#define M32R_IRQ_SIO0_R (40) /* SIO0 send */
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#define M32R_IRQ_SIO0_S (41) /* SIO0 receive */
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#define M32R_IRQ_SIO1_R (42) /* SIO1 send */
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#define M32R_IRQ_SIO1_S (43) /* SIO1 receive */
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#define M32R_IRQ_SIO2_R (44) /* SIO2 send */
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#define M32R_IRQ_SIO2_S (45) /* SIO2 receive */
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#define M32R_IRQ_SIO3_R (46) /* SIO3 send */
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#define M32R_IRQ_SIO3_S (47) /* SIO3 receive */
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#define M32R_IRQ_ADC (56) /* ADC */
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#define M32R_IRQ_PC (57) /* PC */
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#else /* ! M32104 */
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#define M32R_IRQ_DMA0 (32) /* DMA0 */
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#define M32R_IRQ_DMA1 (33) /* DMA1 */
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#define M32R_IRQ_SIO0_R (48) /* SIO0 send */
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#define M32R_IRQ_SIO0_S (49) /* SIO0 receive */
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#define M32R_IRQ_SIO1_R (50) /* SIO1 send */
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#define M32R_IRQ_SIO1_S (51) /* SIO1 receive */
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#define M32R_IRQ_SIO2_R (52) /* SIO2 send */
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#define M32R_IRQ_SIO2_S (53) /* SIO2 receive */
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#define M32R_IRQ_SIO3_R (54) /* SIO3 send */
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#define M32R_IRQ_SIO3_S (55) /* SIO3 receive */
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#define M32R_IRQ_SIO4_R (56) /* SIO4 send */
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#define M32R_IRQ_SIO4_S (57) /* SIO4 receive */
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#endif /* ! M32104 */
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#ifdef CONFIG_SMP
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#define M32R_IRQ_IPI0 (56)
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#define M32R_IRQ_IPI1 (57)
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#define M32R_IRQ_IPI2 (58)
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#define M32R_IRQ_IPI3 (59)
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#define M32R_IRQ_IPI4 (60)
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#define M32R_IRQ_IPI5 (61)
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#define M32R_IRQ_IPI6 (62)
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#define M32R_IRQ_IPI7 (63)
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#define M32R_CPUID_PORTL (0xffffffe0)
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#define M32R_FPGA_TOP (0x000F0000+M32R_SFR_OFFSET)
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#define M32R_FPGA_NUM_OF_CPUS_PORTL (0x00+M32R_FPGA_TOP)
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#define M32R_FPGA_CPU_NAME0_PORTL (0x10+M32R_FPGA_TOP)
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#define M32R_FPGA_CPU_NAME1_PORTL (0x14+M32R_FPGA_TOP)
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#define M32R_FPGA_CPU_NAME2_PORTL (0x18+M32R_FPGA_TOP)
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#define M32R_FPGA_CPU_NAME3_PORTL (0x1c+M32R_FPGA_TOP)
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#define M32R_FPGA_MODEL_ID0_PORTL (0x20+M32R_FPGA_TOP)
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#define M32R_FPGA_MODEL_ID1_PORTL (0x24+M32R_FPGA_TOP)
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#define M32R_FPGA_MODEL_ID2_PORTL (0x28+M32R_FPGA_TOP)
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#define M32R_FPGA_MODEL_ID3_PORTL (0x2c+M32R_FPGA_TOP)
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#define M32R_FPGA_VERSION0_PORTL (0x30+M32R_FPGA_TOP)
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#define M32R_FPGA_VERSION1_PORTL (0x34+M32R_FPGA_TOP)
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#endif /* CONFIG_SMP */
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#ifndef __ASSEMBLY__
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typedef struct {
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unsigned long icucr; /* ICU Control Register */
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} icu_data_t;
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#endif
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#endif /* _M32102_H_ */
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