forked from Minki/linux
771fe6b912
Add kernel modesetting support to radeon driver, use the ttm memory
manager to manage memory and DRM/GEM to provide userspace API.
In order to avoid backward compatibility issue and to allow clean
design and code the radeon kernel modesetting use different code path
than old radeon/drm driver.
When kernel modesetting is enabled the IOCTL of radeon/drm
driver are considered as invalid and an error message is printed
in the log and they return failure.
KMS enabled userspace will use new API to talk with the radeon/drm
driver. The new API provide functions to create/destroy/share/mmap
buffer object which are then managed by the kernel memory manager
(here TTM). In order to submit command to the GPU the userspace
provide a buffer holding the command stream, along this buffer
userspace have to provide a list of buffer object used by the
command stream. The kernel radeon driver will then place buffer
in GPU accessible memory and will update command stream to reflect
the position of the different buffers.
The kernel will also perform security check on command stream
provided by the user, we want to catch and forbid any illegal use
of the GPU such as DMA into random system memory or into memory
not owned by the process supplying the command stream. This part
of the code is still incomplete and this why we propose that patch
as a staging driver addition, future security might forbid current
experimental userspace to run.
This code support the following hardware : R1XX,R2XX,R3XX,R4XX,R5XX
(radeon up to X1950). Works is underway to provide support for R6XX,
R7XX and newer hardware (radeon from HD2XXX to HD4XXX).
Authors:
Jerome Glisse <jglisse@redhat.com>
Dave Airlie <airlied@redhat.com>
Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
250 lines
8.8 KiB
C
250 lines
8.8 KiB
C
/*
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Dave Airlie
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* Jerome Glisse <glisse@freedesktop.org>
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "radeon.h"
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#include "radeon_drm.h"
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#if __OS_HAS_AGP
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struct radeon_agpmode_quirk {
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u32 hostbridge_vendor;
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u32 hostbridge_device;
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u32 chip_vendor;
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u32 chip_device;
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u32 subsys_vendor;
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u32 subsys_device;
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u32 default_mode;
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};
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static struct radeon_agpmode_quirk radeon_agpmode_quirk_list[] = {
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/* Intel E7505 Memory Controller Hub / RV350 AR [Radeon 9600XT] Needs AGPMode 4 (deb #515326) */
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{ PCI_VENDOR_ID_INTEL, 0x2550, PCI_VENDOR_ID_ATI, 0x4152, 0x1458, 0x4038, 4},
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/* Intel 82865G/PE/P DRAM Controller/Host-Hub / Mobility 9800 Needs AGPMode 4 (deb #462590) */
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{ PCI_VENDOR_ID_INTEL, 0x2570, PCI_VENDOR_ID_ATI, 0x4a4e, PCI_VENDOR_ID_DELL, 0x5106, 4},
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/* Intel 82865G/PE/P DRAM Controller/Host-Hub / RV280 [Radeon 9200 SE] Needs AGPMode 4 (lp #300304) */
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{ PCI_VENDOR_ID_INTEL, 0x2570, PCI_VENDOR_ID_ATI, 0x5964,
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0x148c, 0x2073, 4},
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/* Intel 82855PM Processor to I/O Controller / Mobility M6 LY Needs AGPMode 1 (deb #467235) */
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{ PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4c59,
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PCI_VENDOR_ID_IBM, 0x052f, 1},
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/* Intel 82855PM host bridge / Mobility 9600 M10 RV350 Needs AGPMode 1 (lp #195051) */
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{ PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4e50,
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PCI_VENDOR_ID_IBM, 0x0550, 1},
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/* Intel 82855PM host bridge / Mobility M7 needs AGPMode 1 */
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{ PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4c57,
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PCI_VENDOR_ID_IBM, 0x0530, 1},
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/* Intel 82855PM host bridge / FireGL Mobility T2 RV350 Needs AGPMode 2 (fdo #20647) */
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{ PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x4e54,
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PCI_VENDOR_ID_IBM, 0x054f, 2},
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/* Intel 82855PM host bridge / Mobility M9+ / VaioPCG-V505DX Needs AGPMode 2 (fdo #17928) */
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{ PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x5c61,
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PCI_VENDOR_ID_SONY, 0x816b, 2},
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/* Intel 82855PM Processor to I/O Controller / Mobility M9+ Needs AGPMode 8 (phoronix forum) */
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{ PCI_VENDOR_ID_INTEL, 0x3340, PCI_VENDOR_ID_ATI, 0x5c61,
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PCI_VENDOR_ID_SONY, 0x8195, 8},
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/* Intel 82830 830 Chipset Host Bridge / Mobility M6 LY Needs AGPMode 2 (fdo #17360)*/
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{ PCI_VENDOR_ID_INTEL, 0x3575, PCI_VENDOR_ID_ATI, 0x4c59,
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PCI_VENDOR_ID_DELL, 0x00e3, 2},
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/* Intel 82852/82855 host bridge / Mobility FireGL 9000 R250 Needs AGPMode 1 (lp #296617) */
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{ PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4c66,
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PCI_VENDOR_ID_DELL, 0x0149, 1},
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/* Intel 82852/82855 host bridge / Mobility 9600 M10 RV350 Needs AGPMode 1 (deb #467460) */
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{ PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4e50,
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0x1025, 0x0061, 1},
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/* Intel 82852/82855 host bridge / Mobility 9600 M10 RV350 Needs AGPMode 1 (lp #203007) */
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{ PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4e50,
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0x1025, 0x0064, 1},
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/* Intel 82852/82855 host bridge / Mobility 9600 M10 RV350 Needs AGPMode 1 (lp #141551) */
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{ PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4e50,
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PCI_VENDOR_ID_ASUSTEK, 0x1942, 1},
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/* Intel 82852/82855 host bridge / Mobility 9600/9700 Needs AGPMode 1 (deb #510208) */
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{ PCI_VENDOR_ID_INTEL, 0x3580, PCI_VENDOR_ID_ATI, 0x4e50,
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0x10cf, 0x127f, 1},
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/* ASRock K7VT4A+ AGP 8x / ATI Radeon 9250 AGP Needs AGPMode 4 (lp #133192) */
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{ 0x1849, 0x3189, PCI_VENDOR_ID_ATI, 0x5960,
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0x1787, 0x5960, 4},
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/* VIA K8M800 Host Bridge / RV280 [Radeon 9200 PRO] Needs AGPMode 4 (fdo #12544) */
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{ PCI_VENDOR_ID_VIA, 0x0204, PCI_VENDOR_ID_ATI, 0x5960,
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0x17af, 0x2020, 4},
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/* VIA KT880 Host Bridge / RV350 [Radeon 9550] Needs AGPMode 4 (fdo #19981) */
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{ PCI_VENDOR_ID_VIA, 0x0269, PCI_VENDOR_ID_ATI, 0x4153,
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PCI_VENDOR_ID_ASUSTEK, 0x003c, 4},
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/* VIA VT8363 Host Bridge / R200 QL [Radeon 8500] Needs AGPMode 2 (lp #141551) */
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{ PCI_VENDOR_ID_VIA, 0x0305, PCI_VENDOR_ID_ATI, 0x514c,
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PCI_VENDOR_ID_ATI, 0x013a, 2},
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/* VIA VT82C693A Host Bridge / RV280 [Radeon 9200 PRO] Needs AGPMode 2 (deb #515512) */
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{ PCI_VENDOR_ID_VIA, 0x0691, PCI_VENDOR_ID_ATI, 0x5960,
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PCI_VENDOR_ID_ASUSTEK, 0x004c, 2},
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/* VIA VT82C693A Host Bridge / RV280 [Radeon 9200 PRO] Needs AGPMode 2 */
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{ PCI_VENDOR_ID_VIA, 0x0691, PCI_VENDOR_ID_ATI, 0x5960,
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PCI_VENDOR_ID_ASUSTEK, 0x0054, 2},
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/* VIA VT8377 Host Bridge / R200 QM [Radeon 9100] Needs AGPMode 4 (deb #461144) */
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{ PCI_VENDOR_ID_VIA, 0x3189, PCI_VENDOR_ID_ATI, 0x514d,
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0x174b, 0x7149, 4},
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/* VIA VT8377 Host Bridge / RV280 [Radeon 9200 PRO] Needs AGPMode 4 (lp #312693) */
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{ PCI_VENDOR_ID_VIA, 0x3189, PCI_VENDOR_ID_ATI, 0x5960,
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0x1462, 0x0380, 4},
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/* VIA VT8377 Host Bridge / RV280 Needs AGPMode 4 (ati ML) */
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{ PCI_VENDOR_ID_VIA, 0x3189, PCI_VENDOR_ID_ATI, 0x5964,
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0x148c, 0x2073, 4},
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/* ATI Host Bridge / RV280 [M9+] Needs AGPMode 1 (phoronix forum) */
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{ PCI_VENDOR_ID_ATI, 0xcbb2, PCI_VENDOR_ID_ATI, 0x5c61,
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PCI_VENDOR_ID_SONY, 0x8175, 1},
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/* HP Host Bridge / R300 [FireGL X1] Needs AGPMode 2 (fdo #7770) */
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{ PCI_VENDOR_ID_HP, 0x122e, PCI_VENDOR_ID_ATI, 0x4e47,
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PCI_VENDOR_ID_ATI, 0x0152, 2},
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{ 0, 0, 0, 0, 0, 0, 0 },
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};
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#endif
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int radeon_agp_init(struct radeon_device *rdev)
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{
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#if __OS_HAS_AGP
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struct radeon_agpmode_quirk *p = radeon_agpmode_quirk_list;
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struct drm_agp_mode mode;
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struct drm_agp_info info;
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uint32_t agp_status;
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int default_mode;
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bool is_v3;
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int ret;
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/* Acquire AGP. */
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if (!rdev->ddev->agp->acquired) {
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ret = drm_agp_acquire(rdev->ddev);
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if (ret) {
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DRM_ERROR("Unable to acquire AGP: %d\n", ret);
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return ret;
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}
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}
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ret = drm_agp_info(rdev->ddev, &info);
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if (ret) {
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DRM_ERROR("Unable to get AGP info: %d\n", ret);
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return ret;
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}
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mode.mode = info.mode;
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agp_status = (RREG32(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode.mode;
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is_v3 = !!(agp_status & RADEON_AGPv3_MODE);
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if (is_v3) {
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default_mode = (agp_status & RADEON_AGPv3_8X_MODE) ? 8 : 4;
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} else {
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if (agp_status & RADEON_AGP_4X_MODE) {
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default_mode = 4;
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} else if (agp_status & RADEON_AGP_2X_MODE) {
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default_mode = 2;
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} else {
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default_mode = 1;
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}
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}
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/* Apply AGPMode Quirks */
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while (p && p->chip_device != 0) {
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if (info.id_vendor == p->hostbridge_vendor &&
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info.id_device == p->hostbridge_device &&
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rdev->pdev->vendor == p->chip_vendor &&
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rdev->pdev->device == p->chip_device &&
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rdev->pdev->subsystem_vendor == p->subsys_vendor &&
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rdev->pdev->subsystem_device == p->subsys_device) {
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default_mode = p->default_mode;
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}
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++p;
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}
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if (radeon_agpmode > 0) {
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if ((radeon_agpmode < (is_v3 ? 4 : 1)) ||
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(radeon_agpmode > (is_v3 ? 8 : 4)) ||
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(radeon_agpmode & (radeon_agpmode - 1))) {
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DRM_ERROR("Illegal AGP Mode: %d (valid %s), leaving at %d\n",
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radeon_agpmode, is_v3 ? "4, 8" : "1, 2, 4",
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default_mode);
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radeon_agpmode = default_mode;
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} else {
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DRM_INFO("AGP mode requested: %d\n", radeon_agpmode);
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}
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} else {
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radeon_agpmode = default_mode;
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}
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mode.mode &= ~RADEON_AGP_MODE_MASK;
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if (is_v3) {
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switch (radeon_agpmode) {
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case 8:
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mode.mode |= RADEON_AGPv3_8X_MODE;
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break;
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case 4:
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default:
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mode.mode |= RADEON_AGPv3_4X_MODE;
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break;
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}
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} else {
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switch (radeon_agpmode) {
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case 4:
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mode.mode |= RADEON_AGP_4X_MODE;
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break;
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case 2:
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mode.mode |= RADEON_AGP_2X_MODE;
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break;
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case 1:
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default:
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mode.mode |= RADEON_AGP_1X_MODE;
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break;
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}
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}
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mode.mode &= ~RADEON_AGP_FW_MODE; /* disable fw */
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ret = drm_agp_enable(rdev->ddev, mode);
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if (ret) {
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DRM_ERROR("Unable to enable AGP (mode = 0x%lx)\n", mode.mode);
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return ret;
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}
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rdev->mc.agp_base = rdev->ddev->agp->agp_info.aper_base;
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rdev->mc.gtt_size = rdev->ddev->agp->agp_info.aper_size << 20;
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/* workaround some hw issues */
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if (rdev->family < CHIP_R200) {
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WREG32(RADEON_AGP_CNTL, RREG32(RADEON_AGP_CNTL) | 0x000e0000);
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}
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return 0;
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#else
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return 0;
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#endif
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}
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void radeon_agp_fini(struct radeon_device *rdev)
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{
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#if __OS_HAS_AGP
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if (rdev->flags & RADEON_IS_AGP) {
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if (rdev->ddev->agp && rdev->ddev->agp->acquired) {
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drm_agp_release(rdev->ddev);
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}
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}
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#endif
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}
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