leandrof/linux
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
508f5fcb54
linux/drivers/gpu/drm/amd/display/dc/dce
History
Leo Li 508f5fcb54 drm/amd/display: Compensate for XGMI SS downspread on dprefclk 
[Why]
When XGMI is enabled, we need to adjust the dprefclk according to the
WAFL link's spread spectrum info. This is for VG20 (DCE121) only.

[How]
dce_clk_mgr already stores SS info, currently being used by audio clock.
Therefore, patch the clk_mgr's SS info with the xGMI SS info, if xGMI
is enabled. For display clock, adjust it during dce12_update_clocks()
before calling set_clock().

Since we rely on a mmhub register to reliably determine if xGMI is
enabled, the patching step needs to happen after resource_construct()
has initialized the hardware sequencer.

Signed-off-by: Leo Li <sunpeng.li@amd.com>
Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-14 15:04:41 -05:00
..
dce_abm.c drm/amd/display: Expose target backlight level 2018-11-05 14:21:43 -05:00
dce_abm.h drm/amd/display: Fix check for whether dmcu fw is running 2017-12-20 14:46:32 -05:00
dce_audio.c drm/amd/display: Add Dynamic debug prints 2018-04-11 13:08:05 -05:00
dce_audio.h drm/amd/display: Surface Validation Fixes + Audio Mask 2017-09-26 17:16:14 -04:00
dce_aux.c drm/amd/display: Use proper enums in process_channel_reply 2018-10-09 17:04:22 -05:00
dce_aux.h drm/amd/display: flatten aux_engine and engine 2018-07-27 09:07:42 -05:00
dce_clk_mgr.c drm/amd/display: Compensate for XGMI SS downspread on dprefclk 2019-01-14 15:04:41 -05:00
dce_clk_mgr.h drm/amd/display: Compensate for XGMI SS downspread on dprefclk 2019-01-14 15:04:41 -05:00
dce_clock_source.c drm/amd/display: Use 100 Hz precision for pipe pixel clocks 2019-01-14 15:04:39 -05:00
dce_clock_source.h drm/amd/display: stop using switch for different CS revisions 2018-09-14 15:47:11 -05:00
dce_dmcu.c Revert "drm/amdgpu/display: Replace CONFIG_DRM_AMD_DC_DCN1_0 with CONFIG_X86" 2018-08-21 14:32:28 -05:00
dce_dmcu.h drm/amd/display: Enable backlight support for pre-DCE11 ASICs 2018-03-14 15:08:46 -05:00
dce_hwseq.c drm/amd/display: remove dummy is_blanked() to optimise boot time 2018-05-15 13:43:07 -05:00
dce_hwseq.h drm/amd/display: Compensate for XGMI SS downspread on dprefclk 2019-01-14 15:04:41 -05:00
dce_i2c_hw.c drm/amd/display: Flatten unnecessary i2c functions 2018-08-27 15:21:11 -05:00
dce_i2c_hw.h drm/amd/display: Remove redundant i2c structs 2018-08-27 15:20:56 -05:00
dce_i2c_sw.c drm/amd/display: Remove redundant i2c structs 2018-08-27 15:20:56 -05:00
dce_i2c_sw.h drm/amd/display: Create new i2c resource 2018-08-27 11:11:05 -05:00
dce_i2c.c drm/amd/display: Create new i2c resource 2018-08-27 11:11:05 -05:00
dce_i2c.h drm/amd/display: Remove redundant i2c structs 2018-08-27 15:20:56 -05:00
dce_ipp.c drm/amd/display: get rid of 32.32 unsigned fixed point 2018-05-18 16:08:21 -05:00
dce_ipp.h drm/amd/display: dce80, 100, 110 and 112 to dce ipp refactor 2017-09-26 18:06:39 -04:00
dce_link_encoder.c drm/amd/display: Use 100 Hz precision for pipe pixel clocks 2019-01-14 15:04:39 -05:00
dce_link_encoder.h drm/amdgpu/display: add support for LVDS (v5) 2018-08-27 11:11:15 -05:00
dce_mem_input.c drm/amd/display: make function tables const 2018-07-10 14:17:11 -05:00
dce_mem_input.h drm/amd/display: Separate mem input constuctors for dce 112 and 120 2018-04-11 13:07:42 -05:00
dce_opp.c drm/amd/display: Fix FMT truncation programming 2018-03-21 00:22:35 -05:00
dce_opp.h amdgpu/dc: make opp construct void. 2017-09-29 13:01:42 -04:00
dce_scl_filters.c drm/amd/display: get rid of 32.32 unsigned fixed point 2018-05-18 16:08:21 -05:00
dce_stream_encoder.c drm/amd/display: Use 100 Hz precision for pipe pixel clocks 2019-01-14 15:04:39 -05:00
dce_stream_encoder.h amdgpu/dc: make stream encoder constructor return void. 2017-09-29 13:01:29 -04:00
dce_transform.c drm/amd/display: add HDR visual confirm 2018-07-16 16:11:49 -05:00
dce_transform.h drm/amd/display: Add regamma lut write mask to SOC base 2018-03-05 15:34:10 -05:00
Makefile drm/amd/display: rename dccg to clk_mgr 2018-11-05 14:20:48 -05:00