forked from Minki/linux
fba9569924
* 'next' of git://git.infradead.org/users/vkoul/slave-dma: (63 commits)
dmaengine: mid_dma: mask_peripheral_interrupt only when dmac is idle
dmaengine/ep93xx_dma: add module.h include
pch_dma: Reduce wasting memory
pch_dma: Fix suspend issue
dma/timberdale: free_irq() on an error path
dma: shdma: transfer based runtime PM
dmaengine: shdma: protect against the IRQ handler
dmaengine i.MX DMA/SDMA: add missing include of linux/module.h
dmaengine: delete redundant chan_id and chancnt initialization in dma drivers
dmaengine/amba-pl08x: Check txd->llis_va before freeing dma_pool
dmaengine/amba-pl08x: Add support for sg len greater than one for slave transfers
serial: sh-sci: don't filter on DMA device, use only channel ID
ARM: SAMSUNG: Remove Samsung specific enum type for dma direction
ASoC: Samsung: Update DMA interface
spi/s3c64xx: Merge dma control code
spi/s3c64xx: Add support DMA engine API
ARM: SAMSUNG: Remove S3C-PL330-DMA driver
ARM: S5P64X0: Use generic DMA PL330 driver
ARM: S5PC100: Use generic DMA PL330 driver
ARM: S5PV210: Use generic DMA PL330 driver
...
Fix up fairly trivial conflicts in
- arch/arm/mach-exynos4/{Kconfig,clock.c}
- arch/arm/mach-s5p64x0/dma.c
240 lines
5.1 KiB
C
240 lines
5.1 KiB
C
/* linux/arch/arm/mach-s5p64x0/dma.c
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*
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* Copyright (c) 2010 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Copyright (C) 2010 Samsung Electronics Co. Ltd.
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* Jaswinder Singh <jassi.brar@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/dma-mapping.h>
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#include <linux/amba/bus.h>
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#include <linux/amba/pl330.h>
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#include <asm/irq.h>
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#include <mach/map.h>
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#include <mach/irqs.h>
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#include <mach/regs-clock.h>
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#include <mach/dma.h>
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#include <plat/cpu.h>
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#include <plat/devs.h>
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#include <plat/irqs.h>
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static u64 dma_dmamask = DMA_BIT_MASK(32);
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struct dma_pl330_peri s5p6440_pdma_peri[22] = {
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{
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.peri_id = (u8)DMACH_UART0_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_UART0_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_UART1_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_UART1_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_UART2_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_UART2_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_UART3_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_UART3_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = DMACH_MAX,
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}, {
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.peri_id = DMACH_MAX,
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}, {
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.peri_id = (u8)DMACH_PCM0_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_PCM0_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_I2S0_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_I2S0_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_SPI0_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_SPI0_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_MAX,
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}, {
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.peri_id = (u8)DMACH_MAX,
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}, {
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.peri_id = (u8)DMACH_MAX,
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}, {
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.peri_id = (u8)DMACH_MAX,
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}, {
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.peri_id = (u8)DMACH_SPI1_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_SPI1_RX,
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.rqtype = DEVTOMEM,
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},
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};
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struct dma_pl330_platdata s5p6440_pdma_pdata = {
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.nr_valid_peri = ARRAY_SIZE(s5p6440_pdma_peri),
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.peri = s5p6440_pdma_peri,
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};
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struct dma_pl330_peri s5p6450_pdma_peri[32] = {
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{
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.peri_id = (u8)DMACH_UART0_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_UART0_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_UART1_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_UART1_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_UART2_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_UART2_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_UART3_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_UART3_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_UART4_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_UART4_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_PCM0_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_PCM0_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_I2S0_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_I2S0_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_SPI0_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_SPI0_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_PCM1_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_PCM1_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_PCM2_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_PCM2_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_SPI1_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_SPI1_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_USI_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_USI_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_MAX,
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}, {
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.peri_id = (u8)DMACH_I2S1_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_I2S1_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_I2S2_TX,
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.rqtype = MEMTODEV,
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}, {
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.peri_id = (u8)DMACH_I2S2_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_PWM,
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}, {
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.peri_id = (u8)DMACH_UART5_RX,
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.rqtype = DEVTOMEM,
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}, {
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.peri_id = (u8)DMACH_UART5_TX,
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.rqtype = MEMTODEV,
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},
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};
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struct dma_pl330_platdata s5p6450_pdma_pdata = {
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.nr_valid_peri = ARRAY_SIZE(s5p6450_pdma_peri),
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.peri = s5p6450_pdma_peri,
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};
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struct amba_device s5p64x0_device_pdma = {
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.dev = {
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.init_name = "dma-pl330",
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.dma_mask = &dma_dmamask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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.res = {
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.start = S5P64X0_PA_PDMA,
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.end = S5P64X0_PA_PDMA + SZ_4K,
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.flags = IORESOURCE_MEM,
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},
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.irq = {IRQ_DMA0, NO_IRQ},
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.periphid = 0x00041330,
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};
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static int __init s5p64x0_dma_init(void)
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{
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if (soc_is_s5p6450())
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s5p64x0_device_pdma.dev.platform_data = &s5p6450_pdma_pdata;
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else
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s5p64x0_device_pdma.dev.platform_data = &s5p6440_pdma_pdata;
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amba_device_register(&s5p64x0_device_pdma, &iomem_resource);
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return 0;
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}
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arch_initcall(s5p64x0_dma_init);
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