49fe2ba313
Create a new device tree source file for Atmel at91sam9g45 SoC family. The Evaluation Kit at91sam9m10g45ek includes it. This first basic support will be populated as drivers and boards will be converted to device tree. Contains serial, dma and interrupt controllers. The generic board file still takes advantage of platform data for early serial init. As we need a storage media and the NAND flash driver is not converted to DT yet, we keep old initialization for it. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Reviewed-by: Rob Herring <rob.herring@calxeda.com>
123 lines
2.7 KiB
C
123 lines
2.7 KiB
C
/*
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* Setup code for AT91SAM Evaluation Kits with Device Tree support
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*
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* Covers: * AT91SAM9G45-EKES board
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* * AT91SAM9M10-EKES board
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* * AT91SAM9M10G45-EK board
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*
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* Copyright (C) 2011 Atmel,
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* 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
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*
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* Licensed under GPLv2 or later.
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*/
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/gpio.h>
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#include <linux/irqdomain.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <mach/hardware.h>
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#include <mach/board.h>
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#include <mach/system_rev.h>
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#include <mach/at91sam9_smc.h>
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#include <asm/setup.h>
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#include <asm/irq.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/irq.h>
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#include "sam9_smc.h"
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#include "generic.h"
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static void __init ek_init_early(void)
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{
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/* Initialize processor: 12.000 MHz crystal */
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at91_initialize(12000000);
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/* DGBU on ttyS0. (Rx & Tx only) */
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at91_register_uart(0, 0, 0);
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/* set serial console to ttyS0 (ie, DBGU) */
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at91_set_serial_console(0);
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}
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/* det_pin is not connected */
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static struct atmel_nand_data __initdata ek_nand_data = {
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.ale = 21,
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.cle = 22,
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.rdy_pin = AT91_PIN_PC8,
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.enable_pin = AT91_PIN_PC14,
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};
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static struct sam9_smc_config __initdata ek_nand_smc_config = {
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.ncs_read_setup = 0,
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.nrd_setup = 2,
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.ncs_write_setup = 0,
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.nwe_setup = 2,
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.ncs_read_pulse = 4,
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.nrd_pulse = 4,
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.ncs_write_pulse = 4,
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.nwe_pulse = 4,
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.read_cycle = 7,
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.write_cycle = 7,
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.mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
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.tdf_cycles = 3,
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};
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static void __init ek_add_device_nand(void)
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{
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ek_nand_data.bus_width_16 = board_have_nand_16bit();
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/* setup bus-width (8 or 16) */
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if (ek_nand_data.bus_width_16)
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ek_nand_smc_config.mode |= AT91_SMC_DBW_16;
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else
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ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
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/* configure chip-select 3 (NAND) */
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sam9_smc_configure(3, &ek_nand_smc_config);
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at91_add_device_nand(&ek_nand_data);
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}
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static const struct of_device_id aic_of_match[] __initconst = {
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{ .compatible = "atmel,at91rm9200-aic", },
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{},
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};
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static void __init at91_dt_init_irq(void)
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{
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irq_domain_generate_simple(aic_of_match, 0xfffff000, 0);
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at91_init_irq_default();
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}
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static void __init at91_dt_device_init(void)
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{
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of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
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/* NAND */
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ek_add_device_nand();
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}
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static const char *at91_dt_board_compat[] __initdata = {
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"atmel,at91sam9m10g45ek",
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NULL
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};
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DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM (Device Tree)")
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/* Maintainer: Atmel */
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.timer = &at91sam926x_timer,
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.map_io = at91_map_io,
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.init_early = ek_init_early,
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.init_irq = at91_dt_init_irq,
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.init_machine = at91_dt_device_init,
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.dt_compat = at91_dt_board_compat,
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MACHINE_END
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