forked from Minki/linux
f7be9abaa5
Move the core S3C64XX support to mach-s3c64xx as it is unlikely to be used outside of this directory. Also move the SoC header files in with it. This includes the clock, cpu, cpufreq, dma, gpiolib and pll support. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
289 lines
6.3 KiB
C
289 lines
6.3 KiB
C
/* arch/arm/plat-s3c64xx/gpiolib.c
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* S3C64XX - GPIOlib support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <mach/map.h>
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#include <mach/gpio.h>
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#include <plat/gpio-core.h>
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#include <plat/gpio-cfg.h>
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#include <plat/gpio-cfg-helpers.h>
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#include <mach/regs-gpio.h>
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/* GPIO bank summary:
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*
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* Bank GPIOs Style SlpCon ExtInt Group
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* A 8 4Bit Yes 1
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* B 7 4Bit Yes 1
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* C 8 4Bit Yes 2
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* D 5 4Bit Yes 3
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* E 5 4Bit Yes None
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* F 16 2Bit Yes 4 [1]
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* G 7 4Bit Yes 5
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* H 10 4Bit[2] Yes 6
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* I 16 2Bit Yes None
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* J 12 2Bit Yes None
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* K 16 4Bit[2] No None
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* L 15 4Bit[2] No None
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* M 6 4Bit No IRQ_EINT
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* N 16 2Bit No IRQ_EINT
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* O 16 2Bit Yes 7
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* P 15 2Bit Yes 8
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* Q 9 2Bit Yes 9
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*
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* [1] BANKF pins 14,15 do not form part of the external interrupt sources
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* [2] BANK has two control registers, GPxCON0 and GPxCON1
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*/
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static struct s3c_gpio_cfg gpio_4bit_cfg_noint = {
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.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
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.set_pull = s3c_gpio_setpull_updown,
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.get_pull = s3c_gpio_getpull_updown,
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};
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static struct s3c_gpio_cfg gpio_4bit_cfg_eint0111 = {
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.cfg_eint = 7,
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.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
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.set_pull = s3c_gpio_setpull_updown,
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.get_pull = s3c_gpio_getpull_updown,
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};
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static struct s3c_gpio_cfg gpio_4bit_cfg_eint0011 = {
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.cfg_eint = 3,
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.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
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.set_pull = s3c_gpio_setpull_updown,
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.get_pull = s3c_gpio_getpull_updown,
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};
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int s3c64xx_gpio2int_gpm(struct gpio_chip *chip, unsigned pin)
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{
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return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO;
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}
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static struct s3c_gpio_chip gpio_4bit[] = {
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{
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.base = S3C64XX_GPA_BASE,
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.config = &gpio_4bit_cfg_eint0111,
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.chip = {
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.base = S3C64XX_GPA(0),
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.ngpio = S3C64XX_GPIO_A_NR,
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.label = "GPA",
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},
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}, {
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.base = S3C64XX_GPB_BASE,
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.config = &gpio_4bit_cfg_eint0111,
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.chip = {
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.base = S3C64XX_GPB(0),
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.ngpio = S3C64XX_GPIO_B_NR,
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.label = "GPB",
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},
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}, {
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.base = S3C64XX_GPC_BASE,
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.config = &gpio_4bit_cfg_eint0111,
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.chip = {
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.base = S3C64XX_GPC(0),
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.ngpio = S3C64XX_GPIO_C_NR,
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.label = "GPC",
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},
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}, {
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.base = S3C64XX_GPD_BASE,
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.config = &gpio_4bit_cfg_eint0111,
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.chip = {
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.base = S3C64XX_GPD(0),
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.ngpio = S3C64XX_GPIO_D_NR,
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.label = "GPD",
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},
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}, {
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.base = S3C64XX_GPE_BASE,
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.config = &gpio_4bit_cfg_noint,
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.chip = {
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.base = S3C64XX_GPE(0),
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.ngpio = S3C64XX_GPIO_E_NR,
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.label = "GPE",
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},
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}, {
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.base = S3C64XX_GPG_BASE,
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.config = &gpio_4bit_cfg_eint0111,
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.chip = {
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.base = S3C64XX_GPG(0),
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.ngpio = S3C64XX_GPIO_G_NR,
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.label = "GPG",
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},
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}, {
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.base = S3C64XX_GPM_BASE,
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.config = &gpio_4bit_cfg_eint0011,
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.chip = {
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.base = S3C64XX_GPM(0),
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.ngpio = S3C64XX_GPIO_M_NR,
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.label = "GPM",
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.to_irq = s3c64xx_gpio2int_gpm,
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},
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},
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};
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int s3c64xx_gpio2int_gpl(struct gpio_chip *chip, unsigned pin)
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{
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return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO;
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}
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static struct s3c_gpio_chip gpio_4bit2[] = {
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{
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.base = S3C64XX_GPH_BASE + 0x4,
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.config = &gpio_4bit_cfg_eint0111,
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.chip = {
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.base = S3C64XX_GPH(0),
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.ngpio = S3C64XX_GPIO_H_NR,
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.label = "GPH",
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},
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}, {
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.base = S3C64XX_GPK_BASE + 0x4,
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.config = &gpio_4bit_cfg_noint,
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.chip = {
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.base = S3C64XX_GPK(0),
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.ngpio = S3C64XX_GPIO_K_NR,
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.label = "GPK",
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},
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}, {
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.base = S3C64XX_GPL_BASE + 0x4,
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.config = &gpio_4bit_cfg_eint0011,
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.chip = {
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.base = S3C64XX_GPL(0),
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.ngpio = S3C64XX_GPIO_L_NR,
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.label = "GPL",
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.to_irq = s3c64xx_gpio2int_gpl,
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},
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},
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};
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static struct s3c_gpio_cfg gpio_2bit_cfg_noint = {
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.set_config = s3c_gpio_setcfg_s3c24xx,
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.set_pull = s3c_gpio_setpull_updown,
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.get_pull = s3c_gpio_getpull_updown,
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};
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static struct s3c_gpio_cfg gpio_2bit_cfg_eint10 = {
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.cfg_eint = 2,
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.set_config = s3c_gpio_setcfg_s3c24xx,
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.set_pull = s3c_gpio_setpull_updown,
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.get_pull = s3c_gpio_getpull_updown,
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};
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static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = {
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.cfg_eint = 3,
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.set_config = s3c_gpio_setcfg_s3c24xx,
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.set_pull = s3c_gpio_setpull_updown,
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.get_pull = s3c_gpio_getpull_updown,
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};
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int s3c64xx_gpio2int_gpn(struct gpio_chip *chip, unsigned pin)
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{
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return IRQ_EINT(0) + pin;
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}
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static struct s3c_gpio_chip gpio_2bit[] = {
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{
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.base = S3C64XX_GPF_BASE,
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.config = &gpio_2bit_cfg_eint11,
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.chip = {
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.base = S3C64XX_GPF(0),
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.ngpio = S3C64XX_GPIO_F_NR,
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.label = "GPF",
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},
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}, {
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.base = S3C64XX_GPI_BASE,
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.config = &gpio_2bit_cfg_noint,
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.chip = {
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.base = S3C64XX_GPI(0),
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.ngpio = S3C64XX_GPIO_I_NR,
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.label = "GPI",
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},
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}, {
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.base = S3C64XX_GPJ_BASE,
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.config = &gpio_2bit_cfg_noint,
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.chip = {
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.base = S3C64XX_GPJ(0),
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.ngpio = S3C64XX_GPIO_J_NR,
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.label = "GPJ",
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},
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}, {
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.base = S3C64XX_GPN_BASE,
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.config = &gpio_2bit_cfg_eint10,
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.chip = {
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.base = S3C64XX_GPN(0),
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.ngpio = S3C64XX_GPIO_N_NR,
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.label = "GPN",
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.to_irq = s3c64xx_gpio2int_gpn,
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},
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}, {
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.base = S3C64XX_GPO_BASE,
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.config = &gpio_2bit_cfg_eint11,
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.chip = {
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.base = S3C64XX_GPO(0),
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.ngpio = S3C64XX_GPIO_O_NR,
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.label = "GPO",
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},
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}, {
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.base = S3C64XX_GPP_BASE,
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.config = &gpio_2bit_cfg_eint11,
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.chip = {
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.base = S3C64XX_GPP(0),
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.ngpio = S3C64XX_GPIO_P_NR,
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.label = "GPP",
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},
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}, {
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.base = S3C64XX_GPQ_BASE,
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.config = &gpio_2bit_cfg_eint11,
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.chip = {
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.base = S3C64XX_GPQ(0),
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.ngpio = S3C64XX_GPIO_Q_NR,
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.label = "GPQ",
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},
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},
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};
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static __init void s3c64xx_gpiolib_add_2bit(struct s3c_gpio_chip *chip)
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{
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chip->pm = __gpio_pm(&s3c_gpio_pm_2bit);
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}
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static __init void s3c64xx_gpiolib_add(struct s3c_gpio_chip *chips,
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int nr_chips,
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void (*fn)(struct s3c_gpio_chip *))
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{
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for (; nr_chips > 0; nr_chips--, chips++) {
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if (fn)
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(fn)(chips);
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s3c_gpiolib_add(chips);
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}
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}
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static __init int s3c64xx_gpiolib_init(void)
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{
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s3c64xx_gpiolib_add(gpio_4bit, ARRAY_SIZE(gpio_4bit),
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samsung_gpiolib_add_4bit);
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s3c64xx_gpiolib_add(gpio_4bit2, ARRAY_SIZE(gpio_4bit2),
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samsung_gpiolib_add_4bit2);
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s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit),
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s3c64xx_gpiolib_add_2bit);
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return 0;
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}
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core_initcall(s3c64xx_gpiolib_init);
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