linux/arch/xtensa
Max Filippov cd8869f4cb xtensa: add missing isync to the cpu_reset TLB code
ITLB entry modifications must be followed by the isync instruction
before the new entries are possibly used. cpu_reset lacks one isync
between ITLB way 6 initialization and jump to the identity mapping.
Add missing isync to xtensa cpu_reset.

Cc: stable@vger.kernel.org
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2019-08-12 15:05:48 -07:00
..
boot Xtensa updates for v5.3: 2019-07-16 12:17:07 -07:00
configs xtensa: virt: add defconfig and DTS 2019-07-08 14:32:06 -07:00
include Merge branch 'akpm' (patches from Andrew) 2019-07-17 08:58:04 -07:00
kernel xtensa: add missing isync to the cpu_reset TLB code 2019-08-12 15:05:48 -07:00
lib xtensa: abstract 'entry' and 'retw' in assembly code 2019-07-08 10:04:48 -07:00
mm Xtensa updates for v5.3: 2019-07-16 12:17:07 -07:00
oprofile License cleanup: add SPDX GPL-2.0 license identifier to files with no license 2017-11-02 11:10:55 +01:00
platforms treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152 2019-05-30 11:26:32 -07:00
variants xtensa: add test_kc705_be variant 2018-08-20 12:34:45 -07:00
Kconfig binfmt_flat: add a ARCH_HAS_BINFMT_FLAT option 2019-06-24 09:16:47 +10:00
Kconfig.debug Kconfig: consolidate the "Kernel hacking" menu 2018-08-02 08:06:48 +09:00
Makefile xtensa: generate uapi header and syscall table header files 2018-12-02 23:45:41 -08:00