forked from Minki/linux
158ad3260b
ICH3 and ICH4 have undocumented HPET capabilities. This patch enables HPET for platforms based around these ICHs. Tested on various ICH3 and ICH4 platforms. Because HPET is not officially documented for ICH3/4 and may not have been validated by chipset folks, we're on thin ice here. I'd recommend testing this patch in -hrt or -mm for a while and wait for success/failure reports before feeding it upstream. tglx: depends on the force_hpet command line option ! Signed-off-by: Udo A. Steinberg <us15@os.inf.tu-dresden.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
343 lines
8.4 KiB
C
343 lines
8.4 KiB
C
/*
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* This file contains work-arounds for x86 and x86_64 platform bugs.
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*/
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#include <linux/pci.h>
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#include <linux/irq.h>
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#include <asm/hpet.h>
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#if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_SMP) && defined(CONFIG_PCI)
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static void __devinit quirk_intel_irqbalance(struct pci_dev *dev)
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{
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u8 config, rev;
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u32 word;
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/* BIOS may enable hardware IRQ balancing for
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* E7520/E7320/E7525(revision ID 0x9 and below)
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* based platforms.
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* Disable SW irqbalance/affinity on those platforms.
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*/
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pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
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if (rev > 0x9)
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return;
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/* enable access to config space*/
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pci_read_config_byte(dev, 0xf4, &config);
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pci_write_config_byte(dev, 0xf4, config|0x2);
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/* read xTPR register */
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raw_pci_ops->read(0, 0, 0x40, 0x4c, 2, &word);
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if (!(word & (1 << 13))) {
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printk(KERN_INFO "Intel E7520/7320/7525 detected. "
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"Disabling irq balancing and affinity\n");
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#ifdef CONFIG_IRQBALANCE
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irqbalance_disable("");
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#endif
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noirqdebug_setup("");
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#ifdef CONFIG_PROC_FS
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no_irq_affinity = 1;
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#endif
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}
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/* put back the original value for config space*/
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if (!(config & 0x2))
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pci_write_config_byte(dev, 0xf4, config);
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH,
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quirk_intel_irqbalance);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH,
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quirk_intel_irqbalance);
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH,
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quirk_intel_irqbalance);
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#endif
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#if defined(CONFIG_HPET_TIMER)
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unsigned long force_hpet_address;
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static enum {
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NONE_FORCE_HPET_RESUME,
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OLD_ICH_FORCE_HPET_RESUME,
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ICH_FORCE_HPET_RESUME,
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VT8237_FORCE_HPET_RESUME
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} force_hpet_resume_type;
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static void __iomem *rcba_base;
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static void ich_force_hpet_resume(void)
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{
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u32 val;
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if (!force_hpet_address)
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return;
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if (rcba_base == NULL)
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BUG();
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/* read the Function Disable register, dword mode only */
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val = readl(rcba_base + 0x3404);
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if (!(val & 0x80)) {
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/* HPET disabled in HPTC. Trying to enable */
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writel(val | 0x80, rcba_base + 0x3404);
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}
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val = readl(rcba_base + 0x3404);
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if (!(val & 0x80))
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BUG();
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else
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printk(KERN_DEBUG "Force enabled HPET at resume\n");
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return;
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}
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static void ich_force_enable_hpet(struct pci_dev *dev)
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{
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u32 val;
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u32 uninitialized_var(rcba);
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int err = 0;
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if (hpet_address || force_hpet_address)
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return;
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pci_read_config_dword(dev, 0xF0, &rcba);
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rcba &= 0xFFFFC000;
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if (rcba == 0) {
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printk(KERN_DEBUG "RCBA disabled. Cannot force enable HPET\n");
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return;
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}
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/* use bits 31:14, 16 kB aligned */
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rcba_base = ioremap_nocache(rcba, 0x4000);
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if (rcba_base == NULL) {
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printk(KERN_DEBUG "ioremap failed. Cannot force enable HPET\n");
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return;
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}
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/* read the Function Disable register, dword mode only */
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val = readl(rcba_base + 0x3404);
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if (val & 0x80) {
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/* HPET is enabled in HPTC. Just not reported by BIOS */
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val = val & 0x3;
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force_hpet_address = 0xFED00000 | (val << 12);
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printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n",
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force_hpet_address);
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iounmap(rcba_base);
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return;
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}
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/* HPET disabled in HPTC. Trying to enable */
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writel(val | 0x80, rcba_base + 0x3404);
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val = readl(rcba_base + 0x3404);
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if (!(val & 0x80)) {
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err = 1;
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} else {
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val = val & 0x3;
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force_hpet_address = 0xFED00000 | (val << 12);
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}
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if (err) {
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force_hpet_address = 0;
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iounmap(rcba_base);
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printk(KERN_DEBUG "Failed to force enable HPET\n");
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} else {
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force_hpet_resume_type = ICH_FORCE_HPET_RESUME;
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printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n",
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force_hpet_address);
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}
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0,
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ich_force_enable_hpet);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1,
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ich_force_enable_hpet);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0,
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ich_force_enable_hpet);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1,
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ich_force_enable_hpet);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31,
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ich_force_enable_hpet);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1,
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ich_force_enable_hpet);
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static struct pci_dev *cached_dev;
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static void old_ich_force_hpet_resume(void)
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{
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u32 val;
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u32 uninitialized_var(gen_cntl);
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if (!force_hpet_address || !cached_dev)
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return;
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pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
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gen_cntl &= (~(0x7 << 15));
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gen_cntl |= (0x4 << 15);
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pci_write_config_dword(cached_dev, 0xD0, gen_cntl);
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pci_read_config_dword(cached_dev, 0xD0, &gen_cntl);
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val = gen_cntl >> 15;
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val &= 0x7;
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if (val == 0x4)
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printk(KERN_DEBUG "Force enabled HPET at resume\n");
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else
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BUG();
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}
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static void old_ich_force_enable_hpet(struct pci_dev *dev)
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{
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u32 val;
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u32 uninitialized_var(gen_cntl);
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if (hpet_address || force_hpet_address)
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return;
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pci_read_config_dword(dev, 0xD0, &gen_cntl);
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/*
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* Bit 17 is HPET enable bit.
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* Bit 16:15 control the HPET base address.
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*/
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val = gen_cntl >> 15;
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val &= 0x7;
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if (val & 0x4) {
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val &= 0x3;
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force_hpet_address = 0xFED00000 | (val << 12);
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printk(KERN_DEBUG "HPET at base address 0x%lx\n",
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force_hpet_address);
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return;
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}
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/*
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* HPET is disabled. Trying enabling at FED00000 and check
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* whether it sticks
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*/
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gen_cntl &= (~(0x7 << 15));
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gen_cntl |= (0x4 << 15);
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pci_write_config_dword(dev, 0xD0, gen_cntl);
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pci_read_config_dword(dev, 0xD0, &gen_cntl);
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val = gen_cntl >> 15;
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val &= 0x7;
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if (val & 0x4) {
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/* HPET is enabled in HPTC. Just not reported by BIOS */
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val &= 0x3;
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force_hpet_address = 0xFED00000 | (val << 12);
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printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n",
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force_hpet_address);
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cached_dev = dev;
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force_hpet_resume_type = OLD_ICH_FORCE_HPET_RESUME;
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return;
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}
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printk(KERN_DEBUG "Failed to force enable HPET\n");
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}
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/*
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* Undocumented chipset features. Make sure that the user enforced
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* this.
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*/
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static void old_ich_force_enable_hpet_user(struct pci_dev *dev)
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{
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if (hpet_force_user)
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old_ich_force_enable_hpet(dev);
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0,
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old_ich_force_enable_hpet_user);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12,
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old_ich_force_enable_hpet_user);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0,
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old_ich_force_enable_hpet_user);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12,
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old_ich_force_enable_hpet_user);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0,
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old_ich_force_enable_hpet);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_12,
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old_ich_force_enable_hpet);
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static void vt8237_force_hpet_resume(void)
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{
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u32 val;
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if (!force_hpet_address || !cached_dev)
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return;
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val = 0xfed00000 | 0x80;
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pci_write_config_dword(cached_dev, 0x68, val);
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pci_read_config_dword(cached_dev, 0x68, &val);
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if (val & 0x80)
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printk(KERN_DEBUG "Force enabled HPET at resume\n");
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else
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BUG();
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}
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static void vt8237_force_enable_hpet(struct pci_dev *dev)
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{
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u32 uninitialized_var(val);
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if (!hpet_force_user || hpet_address || force_hpet_address)
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return;
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pci_read_config_dword(dev, 0x68, &val);
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/*
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* Bit 7 is HPET enable bit.
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* Bit 31:10 is HPET base address (contrary to what datasheet claims)
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*/
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if (val & 0x80) {
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force_hpet_address = (val & ~0x3ff);
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printk(KERN_DEBUG "HPET at base address 0x%lx\n",
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force_hpet_address);
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return;
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}
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/*
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* HPET is disabled. Trying enabling at FED00000 and check
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* whether it sticks
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*/
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val = 0xfed00000 | 0x80;
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pci_write_config_dword(dev, 0x68, val);
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pci_read_config_dword(dev, 0x68, &val);
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if (val & 0x80) {
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force_hpet_address = (val & ~0x3ff);
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printk(KERN_DEBUG "Force enabled HPET at base address 0x%lx\n",
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force_hpet_address);
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cached_dev = dev;
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force_hpet_resume_type = VT8237_FORCE_HPET_RESUME;
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return;
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}
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printk(KERN_DEBUG "Failed to force enable HPET\n");
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235,
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vt8237_force_enable_hpet);
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237,
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vt8237_force_enable_hpet);
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void force_hpet_resume(void)
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{
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switch (force_hpet_resume_type) {
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case ICH_FORCE_HPET_RESUME:
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return ich_force_hpet_resume();
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case OLD_ICH_FORCE_HPET_RESUME:
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return old_ich_force_hpet_resume();
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case VT8237_FORCE_HPET_RESUME:
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return vt8237_force_hpet_resume();
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default:
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break;
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}
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}
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#endif
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