33e7a97510
Add support for DPT (display page table). DPT is a slightly peculiar two level page table scheme used for tiled scanout buffers (linear uses direct ggtt mapping still). The plane surface address will point at a page in the DPT which holds the PTEs for 512 actual pages. Thus we require 1/512 of the ggttt address space compared to a direct ggtt mapping. We create a new DPT address space for each framebuffer and track two vmas (one for the DPT, another for the ggtt). TODO: - Is the i915_address_space approaach sane? - Maybe don't map the whole DPT to write the PTEs? - Deal with remapping/rotation? Need to create a separate DPT for each remapped/rotated plane I guess. Or else we'd need to make the per-fb DPT large enough to support potentially several remapped/rotated vmas. How large should that be? Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com> Cc: Wilson Chris P <Chris.P.Wilson@intel.com> Cc: Tang CQ <cq.tang@intel.com> Cc: Auld Matthew <matthew.auld@intel.com> Reviewed-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Wilson Chris P <Chris.P.Wilson@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210506161930.309688-5-imre.deak@intel.com
21 lines
386 B
C
21 lines
386 B
C
/* SPDX-License-Identifier: MIT */
|
|
/*
|
|
* Copyright © 2020 Intel Corporation
|
|
*/
|
|
|
|
#ifndef __GEN8_PPGTT_H__
|
|
#define __GEN8_PPGTT_H__
|
|
|
|
#include <linux/kernel.h>
|
|
|
|
struct i915_address_space;
|
|
struct intel_gt;
|
|
enum i915_cache_level;
|
|
|
|
struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt);
|
|
u64 gen8_ggtt_pte_encode(dma_addr_t addr,
|
|
enum i915_cache_level level,
|
|
u32 flags);
|
|
|
|
#endif
|