forked from Minki/linux
0dafafc3ef
Lockdep required a small fix to stacktrace API which was incorrectly unwindign out of __switch_to for the current call frame. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
772 lines
21 KiB
ArmAsm
772 lines
21 KiB
ArmAsm
/*
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* Low Level Interrupts/Traps/Exceptions(non-TLB) Handling for ARC
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*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* vineetg: May 2011
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* -Userspace unaligned access emulation
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*
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* vineetg: Feb 2011 (ptrace low level code fixes)
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* -traced syscall return code (r0) was not saved into pt_regs for restoring
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* into user reg-file when traded task rets to user space.
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* -syscalls needing arch-wrappers (mainly for passing sp as pt_regs)
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* were not invoking post-syscall trace hook (jumping directly into
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* ret_from_system_call)
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*
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* vineetg: Nov 2010:
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* -Vector table jumps (@8 bytes) converted into branches (@4 bytes)
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* -To maintain the slot size of 8 bytes/vector, added nop, which is
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* not executed at runtime.
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*
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* vineetg: Nov 2009 (Everything needed for TIF_RESTORE_SIGMASK)
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* -do_signal()invoked upon TIF_RESTORE_SIGMASK as well
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* -Wrappers for sys_{,rt_}sigsuspend() nolonger needed as they don't
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* need ptregs anymore
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*
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* Vineetg: Oct 2009
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* -In a rare scenario, Process gets a Priv-V exception and gets scheduled
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* out. Since we don't do FAKE RTIE for Priv-V, CPU excpetion state remains
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* active (AE bit enabled). This causes a double fault for a subseq valid
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* exception. Thus FAKE RTIE needed in low level Priv-Violation handler.
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* Instr Error could also cause similar scenario, so same there as well.
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*
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* Vineetg: March 2009 (Supporting 2 levels of Interrupts)
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*
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* Vineetg: Aug 28th 2008: Bug #94984
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* -Zero Overhead Loop Context shd be cleared when entering IRQ/EXcp/Trap
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* Normally CPU does this automatically, however when doing FAKE rtie,
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* we need to explicitly do this. The problem in macros
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* FAKE_RET_FROM_EXCPN and FAKE_RET_FROM_EXCPN_LOCK_IRQ was that this bit
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* was being "CLEARED" rather then "SET". Since it is Loop INHIBIT Bit,
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* setting it and not clearing it clears ZOL context
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*
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* Vineetg: May 16th, 2008
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* - r25 now contains the Current Task when in kernel
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*
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* Vineetg: Dec 22, 2007
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* Minor Surgery of Low Level ISR to make it SMP safe
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* - MMU_SCRATCH0 Reg used for freeing up r9 in Level 1 ISR
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* - _current_task is made an array of NR_CPUS
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* - Access of _current_task wrapped inside a macro so that if hardware
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* team agrees for a dedicated reg, no other code is touched
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*
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* Amit Bhor, Rahul Trivedi, Kanika Nema, Sameer Dhavale : Codito Tech 2004
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*/
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/*------------------------------------------------------------------
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* Function ABI
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*------------------------------------------------------------------
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*
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* Arguments r0 - r7
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* Caller Saved Registers r0 - r12
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* Callee Saved Registers r13- r25
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* Global Pointer (gp) r26
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* Frame Pointer (fp) r27
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* Stack Pointer (sp) r28
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* Interrupt link register (ilink1) r29
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* Interrupt link register (ilink2) r30
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* Branch link register (blink) r31
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*------------------------------------------------------------------
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*/
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.cpu A7
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;############################ Vector Table #################################
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.macro VECTOR lbl
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#if 1 /* Just in case, build breaks */
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j \lbl
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#else
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b \lbl
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nop
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#endif
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.endm
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.section .vector, "ax",@progbits
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.align 4
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/* Each entry in the vector table must occupy 2 words. Since it is a jump
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* across sections (.vector to .text) we are gauranteed that 'j somewhere'
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* will use the 'j limm' form of the intrsuction as long as somewhere is in
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* a section other than .vector.
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*/
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; ********* Critical System Events **********************
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VECTOR res_service ; 0x0, Restart Vector (0x0)
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VECTOR mem_service ; 0x8, Mem exception (0x1)
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VECTOR instr_service ; 0x10, Instrn Error (0x2)
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; ******************** Device ISRs **********************
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#ifdef CONFIG_ARC_IRQ3_LV2
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VECTOR handle_interrupt_level2
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#else
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VECTOR handle_interrupt_level1
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#endif
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VECTOR handle_interrupt_level1
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#ifdef CONFIG_ARC_IRQ5_LV2
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VECTOR handle_interrupt_level2
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#else
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VECTOR handle_interrupt_level1
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#endif
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#ifdef CONFIG_ARC_IRQ6_LV2
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VECTOR handle_interrupt_level2
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#else
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VECTOR handle_interrupt_level1
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#endif
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.rept 25
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VECTOR handle_interrupt_level1 ; Other devices
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.endr
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/* FOR ARC600: timer = 0x3, uart = 0x8, emac = 0x10 */
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; ******************** Exceptions **********************
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VECTOR EV_MachineCheck ; 0x100, Fatal Machine check (0x20)
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VECTOR EV_TLBMissI ; 0x108, Intruction TLB miss (0x21)
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VECTOR EV_TLBMissD ; 0x110, Data TLB miss (0x22)
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VECTOR EV_TLBProtV ; 0x118, Protection Violation (0x23)
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; or Misaligned Access
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VECTOR EV_PrivilegeV ; 0x120, Privilege Violation (0x24)
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VECTOR EV_Trap ; 0x128, Trap exception (0x25)
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VECTOR EV_Extension ; 0x130, Extn Intruction Excp (0x26)
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.rept 24
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VECTOR reserved ; Reserved Exceptions
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.endr
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#include <linux/linkage.h> /* ARC_{EXTRY,EXIT} */
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#include <asm/entry.h> /* SAVE_ALL_{INT1,INT2,SYS...} */
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#include <asm/errno.h>
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#include <asm/arcregs.h>
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#include <asm/irqflags.h>
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;##################### Scratch Mem for IRQ stack switching #############
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ARCFP_DATA int1_saved_reg
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.align 32
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.type int1_saved_reg, @object
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.size int1_saved_reg, 4
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int1_saved_reg:
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.zero 4
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/* Each Interrupt level needs it's own scratch */
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#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
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ARCFP_DATA int2_saved_reg
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.type int2_saved_reg, @object
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.size int2_saved_reg, 4
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int2_saved_reg:
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.zero 4
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#endif
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; ---------------------------------------------
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.section .text, "ax",@progbits
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res_service: ; processor restart
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flag 0x1 ; not implemented
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nop
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nop
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reserved: ; processor restart
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rtie ; jump to processor initializations
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;##################### Interrupt Handling ##############################
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#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
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; ---------------------------------------------
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; Level 2 ISR: Can interrupt a Level 1 ISR
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; ---------------------------------------------
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ARC_ENTRY handle_interrupt_level2
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; TODO-vineetg for SMP this wont work
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; free up r9 as scratchpad
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st r9, [@int2_saved_reg]
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;Which mode (user/kernel) was the system in when intr occured
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lr r9, [status32_l2]
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SWITCH_TO_KERNEL_STK
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SAVE_ALL_INT2
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;------------------------------------------------------
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; if L2 IRQ interrupted a L1 ISR, disable preemption
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;------------------------------------------------------
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ld r9, [sp, PT_status32] ; get statu32_l2 (saved in pt_regs)
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bbit0 r9, STATUS_A1_BIT, 1f ; L1 not active when L2 IRQ, so normal
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; A1 is set in status32_l2
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; bump thread_info->preempt_count (Disable preemption)
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GET_CURR_THR_INFO_FROM_SP r10
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ld r9, [r10, THREAD_INFO_PREEMPT_COUNT]
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add r9, r9, 1
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st r9, [r10, THREAD_INFO_PREEMPT_COUNT]
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1:
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;------------------------------------------------------
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; setup params for Linux common ISR and invoke it
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;------------------------------------------------------
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lr r0, [icause2]
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and r0, r0, 0x1f
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bl.d @arch_do_IRQ
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mov r1, sp
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mov r8,0x2
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sr r8, [AUX_IRQ_LV12] ; clear bit in Sticky Status Reg
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b ret_from_exception
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ARC_EXIT handle_interrupt_level2
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#endif
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; ---------------------------------------------
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; Level 1 ISR
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; ---------------------------------------------
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ARC_ENTRY handle_interrupt_level1
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/* free up r9 as scratchpad */
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#ifdef CONFIG_SMP
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sr r9, [ARC_REG_SCRATCH_DATA0]
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#else
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st r9, [@int1_saved_reg]
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#endif
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;Which mode (user/kernel) was the system in when intr occured
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lr r9, [status32_l1]
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SWITCH_TO_KERNEL_STK
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SAVE_ALL_INT1
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lr r0, [icause1]
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and r0, r0, 0x1f
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#ifdef CONFIG_TRACE_IRQFLAGS
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; icause1 needs to be read early, before calling tracing, which
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; can clobber scratch regs, hence use of stack to stash it
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push r0
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TRACE_ASM_IRQ_DISABLE
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pop r0
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#endif
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bl.d @arch_do_IRQ
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mov r1, sp
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mov r8,0x1
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sr r8, [AUX_IRQ_LV12] ; clear bit in Sticky Status Reg
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b ret_from_exception
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ARC_EXIT handle_interrupt_level1
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;################### Non TLB Exception Handling #############################
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; ---------------------------------------------
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; Instruction Error Exception Handler
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; ---------------------------------------------
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ARC_ENTRY instr_service
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EXCEPTION_PROLOGUE
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lr r0, [efa]
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mov r1, sp
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FAKE_RET_FROM_EXCPN r9
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bl do_insterror_or_kprobe
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b ret_from_exception
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ARC_EXIT instr_service
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; ---------------------------------------------
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; Memory Error Exception Handler
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; ---------------------------------------------
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ARC_ENTRY mem_service
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EXCEPTION_PROLOGUE
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lr r0, [efa]
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mov r1, sp
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FAKE_RET_FROM_EXCPN r9
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bl do_memory_error
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b ret_from_exception
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ARC_EXIT mem_service
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; ---------------------------------------------
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; Machine Check Exception Handler
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; ---------------------------------------------
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ARC_ENTRY EV_MachineCheck
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EXCEPTION_PROLOGUE
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lr r2, [ecr]
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lr r0, [efa]
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mov r1, sp
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lsr r3, r2, 8
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bmsk r3, r3, 7
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brne r3, ECR_C_MCHK_DUP_TLB, 1f
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bl do_tlb_overlap_fault
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b ret_from_exception
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1:
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; DEAD END: can't do much, display Regs and HALT
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SAVE_CALLEE_SAVED_USER
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GET_CURR_TASK_FIELD_PTR TASK_THREAD, r10
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st sp, [r10, THREAD_CALLEE_REG]
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j do_machine_check_fault
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ARC_EXIT EV_MachineCheck
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; ---------------------------------------------
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; Protection Violation Exception Handler
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; ---------------------------------------------
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ARC_ENTRY EV_TLBProtV
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EXCEPTION_PROLOGUE
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;---------(3) Save some more regs-----------------
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; vineetg: Mar 6th: Random Seg Fault issue #1
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; ecr and efa were not saved in case an Intr sneaks in
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; after fake rtie
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lr r2, [ecr]
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lr r0, [efa] ; Faulting Data address
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; --------(4) Return from CPU Exception Mode ---------
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; Fake a rtie, but rtie to next label
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; That way, subsequently, do_page_fault ( ) executes in pure kernel
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; mode with further Exceptions enabled
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FAKE_RET_FROM_EXCPN r9
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mov r1, sp
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;------ (5) Type of Protection Violation? ----------
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;
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; ProtV Hardware Exception is triggered for Access Faults of 2 types
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; -Access Violaton : 00_23_(00|01|02|03)_00
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; x r w r+w
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; -Unaligned Access : 00_23_04_00
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;
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bbit1 r2, ECR_C_BIT_PROTV_MISALIG_DATA, 4f
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;========= (6a) Access Violation Processing ========
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bl do_page_fault
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b ret_from_exception
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;========== (6b) Non aligned access ============
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4:
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SAVE_CALLEE_SAVED_USER
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mov r2, sp ; callee_regs
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bl do_misaligned_access
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; TBD: optimize - do this only if a callee reg was involved
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; either a dst of emulated LD/ST or src with address-writeback
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RESTORE_CALLEE_SAVED_USER
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b ret_from_exception
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ARC_EXIT EV_TLBProtV
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; ---------------------------------------------
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; Privilege Violation Exception Handler
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; ---------------------------------------------
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ARC_ENTRY EV_PrivilegeV
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EXCEPTION_PROLOGUE
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lr r0, [efa]
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mov r1, sp
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FAKE_RET_FROM_EXCPN r9
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bl do_privilege_fault
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b ret_from_exception
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ARC_EXIT EV_PrivilegeV
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; ---------------------------------------------
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; Extension Instruction Exception Handler
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; ---------------------------------------------
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ARC_ENTRY EV_Extension
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EXCEPTION_PROLOGUE
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lr r0, [efa]
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mov r1, sp
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FAKE_RET_FROM_EXCPN r9
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bl do_extension_fault
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b ret_from_exception
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ARC_EXIT EV_Extension
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;######################### System Call Tracing #########################
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tracesys:
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; save EFA in case tracer wants the PC of traced task
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; using ERET won't work since next-PC has already committed
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lr r12, [efa]
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GET_CURR_TASK_FIELD_PTR TASK_THREAD, r11
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st r12, [r11, THREAD_FAULT_ADDR] ; thread.fault_address
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; PRE Sys Call Ptrace hook
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mov r0, sp ; pt_regs needed
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bl @syscall_trace_entry
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; Tracing code now returns the syscall num (orig or modif)
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mov r8, r0
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; Do the Sys Call as we normally would.
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; Validate the Sys Call number
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cmp r8, NR_syscalls
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mov.hi r0, -ENOSYS
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bhi tracesys_exit
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; Restore the sys-call args. Mere invocation of the hook abv could have
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; clobbered them (since they are in scratch regs). The tracer could also
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; have deliberately changed the syscall args: r0-r7
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ld r0, [sp, PT_r0]
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ld r1, [sp, PT_r1]
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ld r2, [sp, PT_r2]
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ld r3, [sp, PT_r3]
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ld r4, [sp, PT_r4]
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ld r5, [sp, PT_r5]
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ld r6, [sp, PT_r6]
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ld r7, [sp, PT_r7]
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ld.as r9, [sys_call_table, r8]
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jl [r9] ; Entry into Sys Call Handler
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tracesys_exit:
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st r0, [sp, PT_r0] ; sys call return value in pt_regs
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;POST Sys Call Ptrace Hook
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bl @syscall_trace_exit
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b ret_from_exception ; NOT ret_from_system_call at is saves r0 which
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; we'd done before calling post hook above
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;################### Break Point TRAP ##########################
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; ======= (5b) Trap is due to Break-Point =========
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trap_with_param:
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; stop_pc info by gdb needs this info
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lr r0, [efa]
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mov r1, sp
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; Now that we have read EFA, its safe to do "fake" rtie
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; and get out of CPU exception mode
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FAKE_RET_FROM_EXCPN r11
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; Save callee regs in case gdb wants to have a look
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; SP will grow up by size of CALLEE Reg-File
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; NOTE: clobbers r12
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SAVE_CALLEE_SAVED_USER
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; save location of saved Callee Regs @ thread_struct->pc
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GET_CURR_TASK_FIELD_PTR TASK_THREAD, r10
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st sp, [r10, THREAD_CALLEE_REG]
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; Call the trap handler
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bl do_non_swi_trap
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; unwind stack to discard Callee saved Regs
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DISCARD_CALLEE_SAVED_USER
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b ret_from_exception
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;##################### Trap Handling ##############################
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;
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; EV_Trap caused by TRAP_S and TRAP0 instructions.
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;------------------------------------------------------------------
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; (1) System Calls
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; :parameters in r0-r7.
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; :r8 has the system call number
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; (2) Break Points
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;------------------------------------------------------------------
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ARC_ENTRY EV_Trap
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EXCEPTION_PROLOGUE
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;------- (4) What caused the Trap --------------
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lr r12, [ecr]
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bmsk.f 0, r12, 7
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bnz trap_with_param
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; ======= (5a) Trap is due to System Call ========
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; Before doing anything, return from CPU Exception Mode
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FAKE_RET_FROM_EXCPN r11
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; If syscall tracing ongoing, invoke pre-pos-hooks
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GET_CURR_THR_INFO_FLAGS r10
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btst r10, TIF_SYSCALL_TRACE
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bnz tracesys ; this never comes back
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;============ This is normal System Call case ==========
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; Sys-call num shd not exceed the total system calls avail
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cmp r8, NR_syscalls
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mov.hi r0, -ENOSYS
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bhi ret_from_system_call
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; Offset into the syscall_table and call handler
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ld.as r9,[sys_call_table, r8]
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jl [r9] ; Entry into Sys Call Handler
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; fall through to ret_from_system_call
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ARC_EXIT EV_Trap
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ARC_ENTRY ret_from_system_call
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st r0, [sp, PT_r0] ; sys call return value in pt_regs
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; fall through yet again to ret_from_exception
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;############# Return from Intr/Excp/Trap (Linux Specifics) ##############
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;
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; If ret to user mode do we need to handle signals, schedule() et al.
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ARC_ENTRY ret_from_exception
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; Pre-{IRQ,Trap,Exception} K/U mode from pt_regs->status32
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ld r8, [sp, PT_status32] ; returning to User/Kernel Mode
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bbit0 r8, STATUS_U_BIT, resume_kernel_mode
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; Before returning to User mode check-for-and-complete any pending work
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; such as rescheduling/signal-delivery etc.
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resume_user_mode_begin:
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; Disable IRQs to ensures that chk for pending work itself is atomic
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; (and we don't end up missing a NEED_RESCHED/SIGPENDING due to an
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; interim IRQ).
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IRQ_DISABLE r10
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; Fast Path return to user mode if no pending work
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GET_CURR_THR_INFO_FLAGS r9
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and.f 0, r9, _TIF_WORK_MASK
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bz restore_regs
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; --- (Slow Path #1) task preemption ---
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bbit0 r9, TIF_NEED_RESCHED, .Lchk_pend_signals
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mov blink, resume_user_mode_begin ; tail-call to U mode ret chks
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b @schedule ; BTST+Bnz causes relo error in link
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.Lchk_pend_signals:
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IRQ_ENABLE r10
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; --- (Slow Path #2) pending signal ---
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mov r0, sp ; pt_regs for arg to do_signal()/do_notify_resume()
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GET_CURR_THR_INFO_FLAGS r9
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bbit0 r9, TIF_SIGPENDING, .Lchk_notify_resume
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; Normal Trap/IRQ entry only saves Scratch (caller-saved) regs
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; in pt_reg since the "C" ABI (kernel code) will automatically
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; save/restore callee-saved regs.
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;
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; However, here we need to explicitly save callee regs because
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; (i) If this signal causes coredump - full regfile needed
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; (ii) If signal is SIGTRAP/SIGSTOP, task is being traced thus
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; tracer might call PEEKUSR(CALLEE reg)
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;
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; NOTE: SP will grow up by size of CALLEE Reg-File
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SAVE_CALLEE_SAVED_USER ; clobbers r12
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; save location of saved Callee Regs @ thread_struct->callee
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GET_CURR_TASK_FIELD_PTR TASK_THREAD, r10
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st sp, [r10, THREAD_CALLEE_REG]
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bl @do_signal
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; Ideally we want to discard the Callee reg above, however if this was
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; a tracing signal, tracer could have done a POKEUSR(CALLEE reg)
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RESTORE_CALLEE_SAVED_USER
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b resume_user_mode_begin ; loop back to start of U mode ret
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; --- (Slow Path #3) notify_resume ---
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.Lchk_notify_resume:
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btst r9, TIF_NOTIFY_RESUME
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blnz @do_notify_resume
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b resume_user_mode_begin ; unconditionally back to U mode ret chks
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; for single exit point from this block
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resume_kernel_mode:
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#ifdef CONFIG_PREEMPT
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; This is a must for preempt_schedule_irq()
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IRQ_DISABLE r9
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; Can't preempt if preemption disabled
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GET_CURR_THR_INFO_FROM_SP r10
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ld r8, [r10, THREAD_INFO_PREEMPT_COUNT]
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brne r8, 0, restore_regs
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; check if this task's NEED_RESCHED flag set
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ld r9, [r10, THREAD_INFO_FLAGS]
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bbit0 r9, TIF_NEED_RESCHED, restore_regs
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; Invoke PREEMPTION
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bl preempt_schedule_irq
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; preempt_schedule_irq() always returns with IRQ disabled
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#endif
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; fall through
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;############# Return from Intr/Excp/Trap (ARC Specifics) ##############
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;
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; Restore the saved sys context (common exit-path for EXCPN/IRQ/Trap)
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; IRQ shd definitely not happen between now and rtie
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; All 2 entry points to here already disable interrupts
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restore_regs :
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TRACE_ASM_IRQ_ENABLE
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lr r10, [status32]
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; Restore REG File. In case multiple Events outstanding,
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; use the same priorty as rtie: EXCPN, L2 IRQ, L1 IRQ, None
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; Note that we use realtime STATUS32 (not pt_regs->status32) to
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; decide that.
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; if Returning from Exception
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bbit0 r10, STATUS_AE_BIT, not_exception
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RESTORE_ALL_SYS
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rtie
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; Not Exception so maybe Interrupts (Level 1 or 2)
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not_exception:
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#ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
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; Level 2 interrupt return Path - from hardware standpoint
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bbit0 r10, STATUS_A2_BIT, not_level2_interrupt
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;------------------------------------------------------------------
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; However the context returning might not have taken L2 intr itself
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; e.g. Task'A' user-code -> L2 intr -> schedule -> 'B' user-code ret
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; Special considerations needed for the context which took L2 intr
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ld r9, [sp, PT_event] ; Ensure this is L2 intr context
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brne r9, event_IRQ2, 149f
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;------------------------------------------------------------------
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; if L2 IRQ interrupted a L1 ISR, we'd disbaled preemption earlier
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; so that sched doesnt move to new task, causing L1 to be delayed
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; undeterministically. Now that we've achieved that, lets reset
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; things to what they were, before returning from L2 context
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;----------------------------------------------------------------
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ld r9, [sp, PT_status32] ; get statu32_l2 (saved in pt_regs)
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bbit0 r9, STATUS_A1_BIT, 149f ; L1 not active when L2 IRQ, so normal
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; decrement thread_info->preempt_count (re-enable preemption)
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GET_CURR_THR_INFO_FROM_SP r10
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ld r9, [r10, THREAD_INFO_PREEMPT_COUNT]
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; paranoid check, given A1 was active when A2 happened, preempt count
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; must not be 0 because we would have incremented it.
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; If this does happen we simply HALT as it means a BUG !!!
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cmp r9, 0
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bnz 2f
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flag 1
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2:
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sub r9, r9, 1
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st r9, [r10, THREAD_INFO_PREEMPT_COUNT]
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149:
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;return from level 2
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RESTORE_ALL_INT2
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debug_marker_l2:
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rtie
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not_level2_interrupt:
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#endif
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bbit0 r10, STATUS_A1_BIT, not_level1_interrupt
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;return from level 1
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RESTORE_ALL_INT1
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debug_marker_l1:
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rtie
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not_level1_interrupt:
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;this case is for syscalls or Exceptions (with fake rtie)
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RESTORE_ALL_SYS
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debug_marker_syscall:
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rtie
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ARC_EXIT ret_from_exception
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ARC_ENTRY ret_from_fork
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; when the forked child comes here from the __switch_to function
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; r0 has the last task pointer.
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; put last task in scheduler queue
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bl @schedule_tail
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; If kernel thread, jump to it's entry-point
|
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ld r9, [sp, PT_status32]
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brne r9, 0, 1f
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|
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jl.d [r14]
|
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mov r0, r13 ; arg to payload
|
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|
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1:
|
|
; special case of kernel_thread entry point returning back due to
|
|
; kernel_execve() - pretend return from syscall to ret to userland
|
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b ret_from_exception
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ARC_EXIT ret_from_fork
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|
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;################### Special Sys Call Wrappers ##########################
|
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|
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ARC_ENTRY sys_clone_wrapper
|
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SAVE_CALLEE_SAVED_USER
|
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bl @sys_clone
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DISCARD_CALLEE_SAVED_USER
|
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|
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GET_CURR_THR_INFO_FLAGS r10
|
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btst r10, TIF_SYSCALL_TRACE
|
|
bnz tracesys_exit
|
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|
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b ret_from_system_call
|
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ARC_EXIT sys_clone_wrapper
|
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|
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#ifdef CONFIG_ARC_DW2_UNWIND
|
|
; Workaround for bug 94179 (STAR ):
|
|
; Despite -fasynchronous-unwind-tables, linker is not making dwarf2 unwinder
|
|
; section (.debug_frame) as loadable. So we force it here.
|
|
; This also fixes STAR 9000487933 where the prev-workaround (objcopy --setflag)
|
|
; would not work after a clean build due to kernel build system dependencies.
|
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.section .debug_frame, "wa",@progbits
|
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#endif
|