3f307963fc
The core clock rate depends on the hw configuration. Once we have read the hardware revision, we can set the core clock to its maximum value. Before then, the clock is set at a rate supported by all MDP5 revisions. Signed-off-by: Stephane Viau <sviau@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com> |
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| drm | ||
| host1x | ||
| ipu-v3 | ||
| vga | ||
| Makefile | ||