forked from Minki/linux
5edafc2982
As reported in [1], rename the k2* dts files to keystone-* files this will force consistency throughout. Script for the same (and hand modified for Makefile and MAINTAINERS files): for i in arch/arm/boot/dts/k2* do b=`basename $i`; git mv $i arch/arm/boot/dts/keystone-$b; sed -i -e "s/$b/keystone-$b/g" arch/arm/boot/dts/*[si] done NOTE: bootloaders that depend on older dtb names will need to be updated as well. [1] http://marc.info/?l=linux-arm-kernel&m=145637407804754&w=2 Reported-by: Olof Johansson <olof@lixom.net> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
78 lines
1.9 KiB
Plaintext
78 lines
1.9 KiB
Plaintext
/*
|
|
* Copyright 2014 Texas Instruments, Inc.
|
|
*
|
|
* Keystone 2 Edison SoC specific device tree
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
|
|
clocks {
|
|
mainpllclk: mainpllclk@2310110 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,keystone,main-pll-clock";
|
|
clocks = <&refclksys>;
|
|
reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
|
|
reg-names = "control", "multiplier", "post-divider";
|
|
};
|
|
|
|
papllclk: papllclk@2620358 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,keystone,pll-clock";
|
|
clocks = <&refclkpass>;
|
|
clock-output-names = "papllclk";
|
|
reg = <0x02620358 4>;
|
|
reg-names = "control";
|
|
};
|
|
|
|
ddr3apllclk: ddr3apllclk@2620360 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,keystone,pll-clock";
|
|
clocks = <&refclkddr3a>;
|
|
clock-output-names = "ddr-3a-pll-clk";
|
|
reg = <0x02620360 4>;
|
|
reg-names = "control";
|
|
};
|
|
|
|
clkusb1: clkusb1 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,keystone,psc-clock";
|
|
clocks = <&chipclk16>;
|
|
clock-output-names = "usb1";
|
|
reg = <0x02350004 0xb00>, <0x02350000 0x400>;
|
|
reg-names = "control", "domain";
|
|
domain-id = <0>;
|
|
};
|
|
|
|
clkhyperlink0: clkhyperlink0 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,keystone,psc-clock";
|
|
clocks = <&chipclk12>;
|
|
clock-output-names = "hyperlink-0";
|
|
reg = <0x02350030 0xb00>, <0x02350014 0x400>;
|
|
reg-names = "control", "domain";
|
|
domain-id = <5>;
|
|
};
|
|
|
|
clkpcie1: clkpcie1 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,keystone,psc-clock";
|
|
clocks = <&chipclk12>;
|
|
clock-output-names = "pcie1";
|
|
reg = <0x0235006c 0xb00>, <0x02350048 0x400>;
|
|
reg-names = "control", "domain";
|
|
domain-id = <18>;
|
|
};
|
|
|
|
clkxge: clkxge {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,keystone,psc-clock";
|
|
clocks = <&chipclk13>;
|
|
clock-output-names = "xge";
|
|
reg = <0x023500c8 0xb00>, <0x02350074 0x400>;
|
|
reg-names = "control", "domain";
|
|
domain-id = <29>;
|
|
};
|
|
};
|