forked from Minki/linux
3b7a17fcda
Now that we return the new resource start position, there is no need to update "struct resource" inside the align function. Therefore, mark the struct resource as const. Cc: Bjorn Helgaas <bjorn.helgaas@hp.com> Cc: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Dominik Brodowski <linux@dominikbrodowski.net> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
417 lines
12 KiB
C
417 lines
12 KiB
C
/*
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* Copyright 2003 PMC-Sierra
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* Author: Manish Lachwani (lachwani@pmc-sierra.com)
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <asm/pci.h>
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#include <asm/io.h>
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#include <linux/init.h>
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#include <asm/titan_dep.h>
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#ifdef CONFIG_HYPERTRANSPORT
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/*
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* This function check if the Hypertransport Link Initialization completed. If
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* it did, then proceed further with scanning bus #2
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*/
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static __inline__ int check_titan_htlink(void)
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{
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u32 val;
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val = *(volatile uint32_t *)(RM9000x2_HTLINK_REG);
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if (val & 0x00000020)
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/* HT Link Initialization completed */
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return 1;
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else
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return 0;
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}
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static int titan_ht_config_read_dword(struct pci_dev *device,
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int offset, u32* val)
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{
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int dev, bus, func;
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uint32_t address_reg, data_reg;
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uint32_t address;
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bus = device->bus->number;
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dev = PCI_SLOT(device->devfn);
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func = PCI_FUNC(device->devfn);
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/* XXX Need to change the Bus # */
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if (bus > 2)
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address = (bus << 16) | (dev << 11) | (func << 8) | (offset & 0xfc) |
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0x80000000 | 0x1;
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else
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address = (dev << 11) | (func << 8) | (offset & 0xfc) | 0x80000000;
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address_reg = RM9000x2_OCD_HTCFGA;
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data_reg = RM9000x2_OCD_HTCFGD;
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RM9K_WRITE(address_reg, address);
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RM9K_READ(data_reg, val);
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return PCIBIOS_SUCCESSFUL;
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}
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static int titan_ht_config_read_word(struct pci_dev *device,
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int offset, u16* val)
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{
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int dev, bus, func;
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uint32_t address_reg, data_reg;
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uint32_t address;
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bus = device->bus->number;
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dev = PCI_SLOT(device->devfn);
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func = PCI_FUNC(device->devfn);
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/* XXX Need to change the Bus # */
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if (bus > 2)
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address = (bus << 16) | (dev << 11) | (func << 8) | (offset & 0xfc) |
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0x80000000 | 0x1;
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else
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address = (dev << 11) | (func << 8) | (offset & 0xfc) | 0x80000000;
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address_reg = RM9000x2_OCD_HTCFGA;
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data_reg = RM9000x2_OCD_HTCFGD;
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if ((offset & 0x3) == 0)
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offset = 0x2;
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else
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offset = 0x0;
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RM9K_WRITE(address_reg, address);
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RM9K_READ_16(data_reg + offset, val);
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return PCIBIOS_SUCCESSFUL;
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}
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u32 longswap(unsigned long l)
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{
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unsigned char b1, b2, b3, b4;
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b1 = l&255;
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b2 = (l>>8)&255;
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b3 = (l>>16)&255;
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b4 = (l>>24)&255;
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return ((b1<<24) + (b2<<16) + (b3<<8) + b4);
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}
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static int titan_ht_config_read_byte(struct pci_dev *device,
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int offset, u8* val)
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{
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int dev, bus, func;
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uint32_t address_reg, data_reg;
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uint32_t address;
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int offset1;
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bus = device->bus->number;
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dev = PCI_SLOT(device->devfn);
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func = PCI_FUNC(device->devfn);
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/* XXX Need to change the Bus # */
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if (bus > 2)
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address = (bus << 16) | (dev << 11) | (func << 8) | (offset & 0xfc) |
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0x80000000 | 0x1;
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else
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address = (dev << 11) | (func << 8) | (offset & 0xfc) | 0x80000000;
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address_reg = RM9000x2_OCD_HTCFGA;
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data_reg = RM9000x2_OCD_HTCFGD;
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RM9K_WRITE(address_reg, address);
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if ((offset & 0x3) == 0) {
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offset1 = 0x3;
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}
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if ((offset & 0x3) == 1) {
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offset1 = 0x2;
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}
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if ((offset & 0x3) == 2) {
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offset1 = 0x1;
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}
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if ((offset & 0x3) == 3) {
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offset1 = 0x0;
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}
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RM9K_READ_8(data_reg + offset1, val);
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return PCIBIOS_SUCCESSFUL;
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}
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static int titan_ht_config_write_dword(struct pci_dev *device,
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int offset, u8 val)
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{
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int dev, bus, func;
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uint32_t address_reg, data_reg;
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uint32_t address;
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bus = device->bus->number;
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dev = PCI_SLOT(device->devfn);
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func = PCI_FUNC(device->devfn);
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/* XXX Need to change the Bus # */
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if (bus > 2)
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address = (bus << 16) | (dev << 11) | (func << 8) | (offset & 0xfc) |
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0x80000000 | 0x1;
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else
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address = (dev << 11) | (func << 8) | (offset & 0xfc) | 0x80000000;
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address_reg = RM9000x2_OCD_HTCFGA;
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data_reg = RM9000x2_OCD_HTCFGD;
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RM9K_WRITE(address_reg, address);
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RM9K_WRITE(data_reg, val);
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return PCIBIOS_SUCCESSFUL;
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}
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static int titan_ht_config_write_word(struct pci_dev *device,
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int offset, u8 val)
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{
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int dev, bus, func;
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uint32_t address_reg, data_reg;
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uint32_t address;
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bus = device->bus->number;
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dev = PCI_SLOT(device->devfn);
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func = PCI_FUNC(device->devfn);
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/* XXX Need to change the Bus # */
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if (bus > 2)
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address = (bus << 16) | (dev << 11) | (func << 8) | (offset & 0xfc) |
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0x80000000 | 0x1;
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else
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address = (dev << 11) | (func << 8) | (offset & 0xfc) | 0x80000000;
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address_reg = RM9000x2_OCD_HTCFGA;
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data_reg = RM9000x2_OCD_HTCFGD;
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if ((offset & 0x3) == 0)
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offset = 0x2;
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else
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offset = 0x0;
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RM9K_WRITE(address_reg, address);
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RM9K_WRITE_16(data_reg + offset, val);
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return PCIBIOS_SUCCESSFUL;
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}
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static int titan_ht_config_write_byte(struct pci_dev *device,
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int offset, u8 val)
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{
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int dev, bus, func;
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uint32_t address_reg, data_reg;
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uint32_t address;
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int offset1;
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bus = device->bus->number;
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dev = PCI_SLOT(device->devfn);
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func = PCI_FUNC(device->devfn);
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/* XXX Need to change the Bus # */
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if (bus > 2)
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address = (bus << 16) | (dev << 11) | (func << 8) | (offset & 0xfc) |
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0x80000000 | 0x1;
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else
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address = (dev << 11) | (func << 8) | (offset & 0xfc) | 0x80000000;
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address_reg = RM9000x2_OCD_HTCFGA;
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data_reg = RM9000x2_OCD_HTCFGD;
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RM9K_WRITE(address_reg, address);
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if ((offset & 0x3) == 0) {
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offset1 = 0x3;
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}
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if ((offset & 0x3) == 1) {
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offset1 = 0x2;
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}
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if ((offset & 0x3) == 2) {
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offset1 = 0x1;
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}
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if ((offset & 0x3) == 3) {
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offset1 = 0x0;
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}
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RM9K_WRITE_8(data_reg + offset1, val);
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return PCIBIOS_SUCCESSFUL;
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}
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static void titan_pcibios_set_master(struct pci_dev *dev)
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{
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u16 cmd;
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int bus = dev->bus->number;
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if (check_titan_htlink())
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titan_ht_config_read_word(dev, PCI_COMMAND, &cmd);
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cmd |= PCI_COMMAND_MASTER;
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if (check_titan_htlink())
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titan_ht_config_write_word(dev, PCI_COMMAND, cmd);
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}
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int pcibios_enable_resources(struct pci_dev *dev)
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{
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u16 cmd, old_cmd;
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u8 tmp1;
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int idx;
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struct resource *r;
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int bus = dev->bus->number;
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if (check_titan_htlink())
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titan_ht_config_read_word(dev, PCI_COMMAND, &cmd);
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old_cmd = cmd;
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for (idx = 0; idx < 6; idx++) {
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r = &dev->resource[idx];
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if (!r->start && r->end) {
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printk(KERN_ERR
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"PCI: Device %s not available because of "
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"resource collisions\n", pci_name(dev));
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return -EINVAL;
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}
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if (r->flags & IORESOURCE_IO)
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cmd |= PCI_COMMAND_IO;
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if (r->flags & IORESOURCE_MEM)
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cmd |= PCI_COMMAND_MEMORY;
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}
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if (cmd != old_cmd) {
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if (check_titan_htlink())
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titan_ht_config_write_word(dev, PCI_COMMAND, cmd);
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}
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if (check_titan_htlink())
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titan_ht_config_read_byte(dev, PCI_CACHE_LINE_SIZE, &tmp1);
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if (tmp1 != 8) {
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printk(KERN_WARNING "PCI setting cache line size to 8 from "
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"%d\n", tmp1);
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}
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if (check_titan_htlink())
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titan_ht_config_write_byte(dev, PCI_CACHE_LINE_SIZE, 8);
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if (check_titan_htlink())
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titan_ht_config_read_byte(dev, PCI_LATENCY_TIMER, &tmp1);
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if (tmp1 < 32 || tmp1 == 0xff) {
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printk(KERN_WARNING "PCI setting latency timer to 32 from %d\n",
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tmp1);
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}
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if (check_titan_htlink())
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titan_ht_config_write_byte(dev, PCI_LATENCY_TIMER, 32);
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return 0;
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}
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int pcibios_enable_device(struct pci_dev *dev, int mask)
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{
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return pcibios_enable_resources(dev);
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}
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resource_size_t pcibios_align_resource(void *data, const struct resource *res,
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resource_size_t size, resource_size_t align)
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{
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struct pci_dev *dev = data;
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resource_size_t start = res->start;
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if (res->flags & IORESOURCE_IO) {
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/* We need to avoid collisions with `mirrored' VGA ports
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and other strange ISA hardware, so we always want the
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addresses kilobyte aligned. */
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if (size > 0x100) {
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printk(KERN_ERR "PCI: I/O Region %s/%d too large"
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" (%ld bytes)\n", pci_name(dev),
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dev->resource - res, size);
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}
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start = (start + 1024 - 1) & ~(1024 - 1);
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}
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return start;
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}
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struct pci_ops titan_pci_ops = {
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titan_ht_config_read_byte,
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titan_ht_config_read_word,
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titan_ht_config_read_dword,
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titan_ht_config_write_byte,
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titan_ht_config_write_word,
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titan_ht_config_write_dword
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};
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void __init pcibios_fixup_bus(struct pci_bus *c)
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{
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titan_ht_pcibios_fixup_bus(c);
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}
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void __init pcibios_init(void)
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{
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/* Reset PCI I/O and PCI MEM values */
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/* XXX Need to add the proper values here */
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ioport_resource.start = 0xe0000000;
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ioport_resource.end = 0xe0000000 + 0x20000000 - 1;
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iomem_resource.start = 0xc0000000;
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iomem_resource.end = 0xc0000000 + 0x20000000 - 1;
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/* XXX Need to add bus values */
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pci_scan_bus(2, &titan_pci_ops, NULL);
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pci_scan_bus(3, &titan_pci_ops, NULL);
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}
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/*
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* for parsing "pci=" kernel boot arguments.
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*/
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char *pcibios_setup(char *str)
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{
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printk(KERN_INFO "rr: pcibios_setup\n");
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/* Nothing to do for now. */
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return str;
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}
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unsigned __init int pcibios_assign_all_busses(void)
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{
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/* We want to use the PCI bus detection done by PMON */
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return 0;
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}
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#endif /* CONFIG_HYPERTRANSPORT */
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